135 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)  in gfx11_kiq_set_resources()  argument
137 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));  in gfx11_kiq_set_resources()
138 	amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |  in gfx11_kiq_set_resources()
140 	amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask));	/* queue mask lo */  in gfx11_kiq_set_resources()
141 	amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask));	/* queue mask hi */  in gfx11_kiq_set_resources()
142 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask lo */  in gfx11_kiq_set_resources()
143 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask hi */  in gfx11_kiq_set_resources()
144 	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */  in gfx11_kiq_set_resources()
145 	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */  in gfx11_kiq_set_resources()
148 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring,  in gfx11_kiq_map_queues()  argument
172 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));  in gfx11_kiq_map_queues()
174 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */  in gfx11_kiq_map_queues()
184 	amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));  in gfx11_kiq_map_queues()
185 	amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));  in gfx11_kiq_map_queues()
186 	amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));  in gfx11_kiq_map_queues()
187 	amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));  in gfx11_kiq_map_queues()
188 	amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));  in gfx11_kiq_map_queues()
191 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,  in gfx11_kiq_unmap_queues()  argument
196 	struct amdgpu_device *adev = kiq_ring->adev;  in gfx11_kiq_unmap_queues()
204 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));  in gfx11_kiq_unmap_queues()
205 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */  in gfx11_kiq_unmap_queues()
210 	amdgpu_ring_write(kiq_ring,  in gfx11_kiq_unmap_queues()
214 		amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));  in gfx11_kiq_unmap_queues()
215 		amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));  in gfx11_kiq_unmap_queues()
216 		amdgpu_ring_write(kiq_ring, seq);  in gfx11_kiq_unmap_queues()
218 		amdgpu_ring_write(kiq_ring, 0);  in gfx11_kiq_unmap_queues()
219 		amdgpu_ring_write(kiq_ring, 0);  in gfx11_kiq_unmap_queues()
220 		amdgpu_ring_write(kiq_ring, 0);  in gfx11_kiq_unmap_queues()
224 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring,  in gfx11_kiq_query_status()  argument
231 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));  in gfx11_kiq_query_status()
232 	amdgpu_ring_write(kiq_ring,  in gfx11_kiq_query_status()
236 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */  in gfx11_kiq_query_status()
239 	amdgpu_ring_write(kiq_ring, lower_32_bits(addr));  in gfx11_kiq_query_status()
240 	amdgpu_ring_write(kiq_ring, upper_32_bits(addr));  in gfx11_kiq_query_status()
241 	amdgpu_ring_write(kiq_ring, lower_32_bits(seq));  in gfx11_kiq_query_status()
242 	amdgpu_ring_write(kiq_ring, upper_32_bits(seq));  in gfx11_kiq_query_status()
245 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,  in gfx11_kiq_invalidate_tlbs()  argument
249 	gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);  in gfx11_kiq_invalidate_tlbs()
5543 	struct amdgpu_ring *kiq_ring = &kiq->ring;  in gfx_v11_0_ring_preempt_ib()  local
5551 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {  in gfx_v11_0_ring_preempt_ib()
5560 	kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,  in gfx_v11_0_ring_preempt_ib()
5563 	amdgpu_ring_commit(kiq_ring);  in gfx_v11_0_ring_preempt_ib()