2047 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_me_cache()
2091 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_pfp_cache()
2166 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_pfp_cache_rs64()
2247 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_pfp_cache_rs64()
2288 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_me_cache_rs64()
2370 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_me_cache_rs64()
2406 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_mec_cache_rs64()
2412 	tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_mec_cache_rs64()
2771 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2852 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2989 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3071 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3494 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3500 	tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3613 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);  in gfx_v11_0_gfx_mqd_init()
3620 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);  in gfx_v11_0_gfx_mqd_init()
3796 	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);  in gfx_v11_0_compute_mqd_init()