147 static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)  in dce_v8_0_vblank_get_counter()  argument
149 	if (crtc >= adev->mode_info.num_crtc)  in dce_v8_0_vblank_get_counter()
152 		return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);  in dce_v8_0_vblank_get_counter()
206 static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,  in dce_v8_0_crtc_get_scanoutpos()  argument
209 	if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))  in dce_v8_0_crtc_get_scanoutpos()
212 	*vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);  in dce_v8_0_crtc_get_scanoutpos()
213 	*position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);  in dce_v8_0_crtc_get_scanoutpos()
450 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);  in dce_v8_0_program_fmt()
1495 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);  in dce_v8_0_audio_set_dto()
1539 	if (encoder->crtc) {  in dce_v8_0_afmt_setmode()
1540 		struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);  in dce_v8_0_afmt_setmode()
1749 static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)  in dce_v8_0_vga_enable()  argument
1751 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_vga_enable()
1752 	struct drm_device *dev = crtc->dev;  in dce_v8_0_vga_enable()
1763 static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)  in dce_v8_0_grph_enable()  argument
1765 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_grph_enable()
1766 	struct drm_device *dev = crtc->dev;  in dce_v8_0_grph_enable()
1775 static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,  in dce_v8_0_crtc_do_set_base()  argument
1779 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_do_set_base()
1780 	struct drm_device *dev = crtc->dev;  in dce_v8_0_crtc_do_set_base()
1794 	if (!atomic && !crtc->primary->fb) {  in dce_v8_0_crtc_do_set_base()
1802 		target_fb = crtc->primary->fb;  in dce_v8_0_crtc_do_set_base()
1929 	dce_v8_0_vga_enable(crtc, false);  in dce_v8_0_crtc_do_set_base()
1969 	dce_v8_0_grph_enable(crtc, true);  in dce_v8_0_crtc_do_set_base()
1978 	viewport_w = crtc->mode.hdisplay;  in dce_v8_0_crtc_do_set_base()
1979 	viewport_h = (crtc->mode.vdisplay + 1) & ~1;  in dce_v8_0_crtc_do_set_base()
1986 	if (!atomic && fb && fb != crtc->primary->fb) {  in dce_v8_0_crtc_do_set_base()
2001 static void dce_v8_0_set_interleave(struct drm_crtc *crtc,  in dce_v8_0_set_interleave()  argument
2004 	struct drm_device *dev = crtc->dev;  in dce_v8_0_set_interleave()
2006 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_set_interleave()
2015 static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)  in dce_v8_0_crtc_load_lut()  argument
2017 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_load_lut()
2018 	struct drm_device *dev = crtc->dev;  in dce_v8_0_crtc_load_lut()
2050 	r = crtc->gamma_store;  in dce_v8_0_crtc_load_lut()
2051 	g = r + crtc->gamma_size;  in dce_v8_0_crtc_load_lut()
2052 	b = g + crtc->gamma_size;  in dce_v8_0_crtc_load_lut()
2133 static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)  in dce_v8_0_pick_pll()  argument
2135 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_pick_pll()
2136 	struct drm_device *dev = crtc->dev;  in dce_v8_0_pick_pll()
2147 			pll = amdgpu_pll_get_shared_dp_ppll(crtc);  in dce_v8_0_pick_pll()
2153 		pll = amdgpu_pll_get_shared_nondp_ppll(crtc);  in dce_v8_0_pick_pll()
2161 		pll_in_use = amdgpu_pll_get_use_mask(crtc);  in dce_v8_0_pick_pll()
2170 		pll_in_use = amdgpu_pll_get_use_mask(crtc);  in dce_v8_0_pick_pll()
2183 static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)  in dce_v8_0_lock_cursor()  argument
2185 	struct amdgpu_device *adev = drm_to_adev(crtc->dev);  in dce_v8_0_lock_cursor()
2186 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_lock_cursor()
2197 static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)  in dce_v8_0_hide_cursor()  argument
2199 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_hide_cursor()
2200 	struct amdgpu_device *adev = drm_to_adev(crtc->dev);  in dce_v8_0_hide_cursor()
2207 static void dce_v8_0_show_cursor(struct drm_crtc *crtc)  in dce_v8_0_show_cursor()  argument
2209 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_show_cursor()
2210 	struct amdgpu_device *adev = drm_to_adev(crtc->dev);  in dce_v8_0_show_cursor()
2223 static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,  in dce_v8_0_cursor_move_locked()  argument
2226 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_cursor_move_locked()
2227 	struct amdgpu_device *adev = drm_to_adev(crtc->dev);  in dce_v8_0_cursor_move_locked()
2234 	x += crtc->x;  in dce_v8_0_cursor_move_locked()
2235 	y += crtc->y;  in dce_v8_0_cursor_move_locked()
2236 	DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);  in dce_v8_0_cursor_move_locked()
2255 static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,  in dce_v8_0_crtc_cursor_move()  argument
2260 	dce_v8_0_lock_cursor(crtc, true);  in dce_v8_0_crtc_cursor_move()
2261 	ret = dce_v8_0_cursor_move_locked(crtc, x, y);  in dce_v8_0_crtc_cursor_move()
2262 	dce_v8_0_lock_cursor(crtc, false);  in dce_v8_0_crtc_cursor_move()
2267 static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,  in dce_v8_0_crtc_cursor_set2()  argument
2275 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_cursor_set2()
2282 		dce_v8_0_hide_cursor(crtc);  in dce_v8_0_crtc_cursor_set2()
2315 	dce_v8_0_lock_cursor(crtc, true);  in dce_v8_0_crtc_cursor_set2()
2326 		dce_v8_0_cursor_move_locked(crtc, x, y);  in dce_v8_0_crtc_cursor_set2()
2334 	dce_v8_0_show_cursor(crtc);  in dce_v8_0_crtc_cursor_set2()
2335 	dce_v8_0_lock_cursor(crtc, false);  in dce_v8_0_crtc_cursor_set2()
2352 static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)  in dce_v8_0_cursor_reset()  argument
2354 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_cursor_reset()
2357 		dce_v8_0_lock_cursor(crtc, true);  in dce_v8_0_cursor_reset()
2359 		dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,  in dce_v8_0_cursor_reset()
2362 		dce_v8_0_show_cursor(crtc);  in dce_v8_0_cursor_reset()
2364 		dce_v8_0_lock_cursor(crtc, false);  in dce_v8_0_cursor_reset()
2368 static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,  in dce_v8_0_crtc_gamma_set()  argument
2372 	dce_v8_0_crtc_load_lut(crtc);  in dce_v8_0_crtc_gamma_set()
2377 static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)  in dce_v8_0_crtc_destroy()  argument
2379 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_destroy()
2381 	drm_crtc_cleanup(crtc);  in dce_v8_0_crtc_destroy()
2398 static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)  in dce_v8_0_crtc_dpms()  argument
2400 	struct drm_device *dev = crtc->dev;  in dce_v8_0_crtc_dpms()
2402 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_dpms()
2408 		amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);  in dce_v8_0_crtc_dpms()
2409 		dce_v8_0_vga_enable(crtc, true);  in dce_v8_0_crtc_dpms()
2410 		amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);  in dce_v8_0_crtc_dpms()
2411 		dce_v8_0_vga_enable(crtc, false);  in dce_v8_0_crtc_dpms()
2417 		drm_crtc_vblank_on(crtc);  in dce_v8_0_crtc_dpms()
2418 		dce_v8_0_crtc_load_lut(crtc);  in dce_v8_0_crtc_dpms()
2423 		drm_crtc_vblank_off(crtc);  in dce_v8_0_crtc_dpms()
2425 			dce_v8_0_vga_enable(crtc, true);  in dce_v8_0_crtc_dpms()
2426 			amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);  in dce_v8_0_crtc_dpms()
2427 			dce_v8_0_vga_enable(crtc, false);  in dce_v8_0_crtc_dpms()
2429 		amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);  in dce_v8_0_crtc_dpms()
2437 static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)  in dce_v8_0_crtc_prepare()  argument
2440 	amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);  in dce_v8_0_crtc_prepare()
2441 	amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);  in dce_v8_0_crtc_prepare()
2442 	dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);  in dce_v8_0_crtc_prepare()
2445 static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)  in dce_v8_0_crtc_commit()  argument
2447 	dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);  in dce_v8_0_crtc_commit()
2448 	amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);  in dce_v8_0_crtc_commit()
2451 static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)  in dce_v8_0_crtc_disable()  argument
2453 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_disable()
2454 	struct drm_device *dev = crtc->dev;  in dce_v8_0_crtc_disable()
2459 	dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);  in dce_v8_0_crtc_disable()
2460 	if (crtc->primary->fb) {  in dce_v8_0_crtc_disable()
2464 		abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);  in dce_v8_0_crtc_disable()
2474 	dce_v8_0_grph_enable(crtc, false);  in dce_v8_0_crtc_disable()
2476 	amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);  in dce_v8_0_crtc_disable()
2494 		amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,  in dce_v8_0_crtc_disable()
2502 			amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,  in dce_v8_0_crtc_disable()
2515 static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,  in dce_v8_0_crtc_mode_set()  argument
2520 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_mode_set()
2525 	amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);  in dce_v8_0_crtc_mode_set()
2526 	amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);  in dce_v8_0_crtc_mode_set()
2527 	dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);  in dce_v8_0_crtc_mode_set()
2528 	amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);  in dce_v8_0_crtc_mode_set()
2529 	amdgpu_atombios_crtc_scaler_setup(crtc);  in dce_v8_0_crtc_mode_set()
2530 	dce_v8_0_cursor_reset(crtc);  in dce_v8_0_crtc_mode_set()
2537 static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,  in dce_v8_0_crtc_mode_fixup()  argument
2541 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  in dce_v8_0_crtc_mode_fixup()
2542 	struct drm_device *dev = crtc->dev;  in dce_v8_0_crtc_mode_fixup()
2547 		if (encoder->crtc == crtc) {  in dce_v8_0_crtc_mode_fixup()
2558 	if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))  in dce_v8_0_crtc_mode_fixup()
2560 	if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))  in dce_v8_0_crtc_mode_fixup()
2563 	amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);  in dce_v8_0_crtc_mode_fixup()
2572 static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,  in dce_v8_0_crtc_set_base()  argument
2575 	return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);  in dce_v8_0_crtc_set_base()
2578 static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,  in dce_v8_0_crtc_set_base_atomic()  argument
2582 	return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);  in dce_v8_0_crtc_set_base_atomic()
2883 						     int crtc,  in dce_v8_0_set_crtc_vblank_interrupt_state()  argument
2888 	if (crtc >= adev->mode_info.num_crtc) {  in dce_v8_0_set_crtc_vblank_interrupt_state()
2889 		DRM_DEBUG("invalid crtc %d\n", crtc);  in dce_v8_0_set_crtc_vblank_interrupt_state()
2893 	switch (crtc) {  in dce_v8_0_set_crtc_vblank_interrupt_state()
2913 		DRM_DEBUG("invalid crtc %d\n", crtc);  in dce_v8_0_set_crtc_vblank_interrupt_state()
2934 						    int crtc,  in dce_v8_0_set_crtc_vline_interrupt_state()  argument
2939 	if (crtc >= adev->mode_info.num_crtc) {  in dce_v8_0_set_crtc_vline_interrupt_state()
2940 		DRM_DEBUG("invalid crtc %d\n", crtc);  in dce_v8_0_set_crtc_vline_interrupt_state()
2944 	switch (crtc) {  in dce_v8_0_set_crtc_vline_interrupt_state()
2964 		DRM_DEBUG("invalid crtc %d\n", crtc);  in dce_v8_0_set_crtc_vline_interrupt_state()
3066 	unsigned crtc = entry->src_id - 1;  in dce_v8_0_crtc_irq()  local
3067 	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);  in dce_v8_0_crtc_irq()
3069 								    crtc);  in dce_v8_0_crtc_irq()
3073 		if (disp_int & interrupt_status_offsets[crtc].vblank)  in dce_v8_0_crtc_irq()
3074 			WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);  in dce_v8_0_crtc_irq()
3079 			drm_handle_vblank(adev_to_drm(adev), crtc);  in dce_v8_0_crtc_irq()
3081 		DRM_DEBUG("IH: D%d vblank\n", crtc + 1);  in dce_v8_0_crtc_irq()
3084 		if (disp_int & interrupt_status_offsets[crtc].vline)  in dce_v8_0_crtc_irq()
3085 			WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);  in dce_v8_0_crtc_irq()
3089 		DRM_DEBUG("IH: D%d vline\n", crtc + 1);  in dce_v8_0_crtc_irq()
3245 	dce_v8_0_set_interleave(encoder->crtc, mode);  in dce_v8_0_encoder_mode_set()