200 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?  in dce_v6_0_page_flip()
203 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,  in dce_v6_0_page_flip()
206 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v6_0_page_flip()
208 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v6_0_page_flip()
212 	RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);  in dce_v6_0_page_flip()
457 	WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v6_0_program_fmt()
960 	arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);  in dce_v6_0_program_watermarks()
964 	WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);  in dce_v6_0_program_watermarks()
965 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_program_watermarks()
969 	tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);  in dce_v6_0_program_watermarks()
972 	WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);  in dce_v6_0_program_watermarks()
973 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_program_watermarks()
977 	WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3);  in dce_v6_0_program_watermarks()
980 	WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt);  in dce_v6_0_program_watermarks()
981 	WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt);  in dce_v6_0_program_watermarks()
1025 	WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset,  in dce_v6_0_line_buffer_adjust()
1806 	WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);  in dce_v6_0_grph_enable()
1965 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_do_set_base()
1967 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
1969 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
1971 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
1973 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
1975 	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);  in dce_v6_0_crtc_do_set_base()
1976 	WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);  in dce_v6_0_crtc_do_set_base()
1983 	WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
1990 	WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_do_set_base()
1991 	WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_do_set_base()
1992 	WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_do_set_base()
1993 	WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_do_set_base()
1994 	WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);  in dce_v6_0_crtc_do_set_base()
1995 	WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);  in dce_v6_0_crtc_do_set_base()
1998 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);  in dce_v6_0_crtc_do_set_base()
2002 	WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
2006 	WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
2011 	WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_do_set_base()
2015 	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_do_set_base()
2041 		WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset,  in dce_v6_0_set_interleave()
2044 		WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_set_interleave()
2058 	WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2061 	WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2063 	WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2065 	WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2069 	WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_load_lut()
2071 	WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_load_lut()
2072 	WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_load_lut()
2073 	WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_load_lut()
2075 	WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v6_0_crtc_load_lut()
2076 	WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v6_0_crtc_load_lut()
2077 	WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v6_0_crtc_load_lut()
2079 	WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_load_lut()
2080 	WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);  in dce_v6_0_crtc_load_lut()
2082 	WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_load_lut()
2087 		WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2093 	WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2098 	WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2101 	WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2104 	WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_crtc_load_lut()
2108 	WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);  in dce_v6_0_crtc_load_lut()
2185 	cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);  in dce_v6_0_lock_cursor()
2190 	WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);  in dce_v6_0_lock_cursor()
2198 	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_hide_cursor()
2210 	WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v6_0_show_cursor()
2212 	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v6_0_show_cursor()
2215 	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,  in dce_v6_0_show_cursor()
2248 	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);  in dce_v6_0_cursor_move_locked()
2249 	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);  in dce_v6_0_cursor_move_locked()
2250 	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,  in dce_v6_0_cursor_move_locked()
2606 	amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];  in dce_v6_0_crtc_init()