264 	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_page_flip()
267 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_page_flip()
269 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,  in dce_v11_0_page_flip()
272 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v11_0_page_flip()
275 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v11_0_page_flip()
278 	RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);  in dce_v11_0_page_flip()
606 	WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_program_fmt()
657 	tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);  in dce_v11_0_line_buffer_adjust()
659 	WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_line_buffer_adjust()
1154 	wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_program_watermarks()
1156 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_program_watermarks()
1157 	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_program_watermarks()
1160 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_program_watermarks()
1163 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_program_watermarks()
1164 	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_program_watermarks()
1167 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_program_watermarks()
1169 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);  in dce_v11_0_program_watermarks()
1887 		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);  in dce_v11_0_grph_enable()
1889 		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_grph_enable()
2065 	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_crtc_do_set_base()
2068 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_crtc_do_set_base()
2070 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v11_0_crtc_do_set_base()
2072 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v11_0_crtc_do_set_base()
2074 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v11_0_crtc_do_set_base()
2076 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v11_0_crtc_do_set_base()
2078 	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);  in dce_v11_0_crtc_do_set_base()
2079 	WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);  in dce_v11_0_crtc_do_set_base()
2086 	tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);  in dce_v11_0_crtc_do_set_base()
2091 	WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_crtc_do_set_base()
2096 	WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_do_set_base()
2097 	WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_do_set_base()
2098 	WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_do_set_base()
2099 	WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_do_set_base()
2100 	WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);  in dce_v11_0_crtc_do_set_base()
2101 	WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);  in dce_v11_0_crtc_do_set_base()
2104 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);  in dce_v11_0_crtc_do_set_base()
2108 	WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,  in dce_v11_0_crtc_do_set_base()
2113 	WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,  in dce_v11_0_crtc_do_set_base()
2117 	WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,  in dce_v11_0_crtc_do_set_base()
2121 	WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_do_set_base()
2146 	tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);  in dce_v11_0_set_interleave()
2151 	WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_set_interleave()
2165 	tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_crtc_load_lut()
2167 	WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_crtc_load_lut()
2169 	tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_crtc_load_lut()
2171 	WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_crtc_load_lut()
2173 	tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_crtc_load_lut()
2175 	WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_crtc_load_lut()
2177 	WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_load_lut()
2179 	WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_load_lut()
2180 	WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_load_lut()
2181 	WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_load_lut()
2183 	WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v11_0_crtc_load_lut()
2184 	WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v11_0_crtc_load_lut()
2185 	WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);  in dce_v11_0_crtc_load_lut()
2187 	WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_load_lut()
2188 	WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);  in dce_v11_0_crtc_load_lut()
2190 	WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_load_lut()
2195 		WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,  in dce_v11_0_crtc_load_lut()
2201 	tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_crtc_load_lut()
2205 	WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_crtc_load_lut()
2207 	tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_crtc_load_lut()
2209 	WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_crtc_load_lut()
2211 	tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_crtc_load_lut()
2213 	WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_crtc_load_lut()
2215 	tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_crtc_load_lut()
2217 	WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_crtc_load_lut()
2220 	WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);  in dce_v11_0_crtc_load_lut()
2224 	tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_crtc_load_lut()
2226 	WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_crtc_load_lut()
2366 	cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);  in dce_v11_0_lock_cursor()
2371 	WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);  in dce_v11_0_lock_cursor()
2380 	tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_hide_cursor()
2382 	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_hide_cursor()
2391 	WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,  in dce_v11_0_show_cursor()
2393 	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  in dce_v11_0_show_cursor()
2396 	tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v11_0_show_cursor()
2399 	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);  in dce_v11_0_show_cursor()
2426 	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);  in dce_v11_0_cursor_move_locked()
2427 	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);  in dce_v11_0_cursor_move_locked()
2428 	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,  in dce_v11_0_cursor_move_locked()
2821 		amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;  in dce_v11_0_crtc_init()
2824 		amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;  in dce_v11_0_crtc_init()
2827 		amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;  in dce_v11_0_crtc_init()
2830 		amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;  in dce_v11_0_crtc_init()
2833 		amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;  in dce_v11_0_crtc_init()
2836 		amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;  in dce_v11_0_crtc_init()