92 	uint32_t        hpd;  member
98 	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
103 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
108 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
113 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
118 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
123 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
294  * dce_v11_0_hpd_sense - hpd sense callback.
297  * @hpd: hpd (hotplug detect) pin
303 			       enum amdgpu_hpd_id hpd)  in dce_v11_0_hpd_sense()  argument
307 	if (hpd >= adev->mode_info.num_hpd)  in dce_v11_0_hpd_sense()
310 	if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &  in dce_v11_0_hpd_sense()
318  * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
321  * @hpd: hpd (hotplug detect) pin
323  * Set the polarity of the hpd pin (evergreen+).
326 				      enum amdgpu_hpd_id hpd)  in dce_v11_0_hpd_set_polarity()  argument
329 	bool connected = dce_v11_0_hpd_sense(adev, hpd);  in dce_v11_0_hpd_set_polarity()
331 	if (hpd >= adev->mode_info.num_hpd)  in dce_v11_0_hpd_set_polarity()
334 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_hpd_set_polarity()
339 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_hpd_set_polarity()
343  * dce_v11_0_hpd_init - hpd setup callback.
347  * Setup the hpd pins used by the card (evergreen+).
348  * Enable the pin, set the polarity, and enable the hpd interrupts.
361 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v11_0_hpd_init()
366 			/* don't try to enable hpd on eDP or LVDS avoid breaking the  in dce_v11_0_hpd_init()
371 			tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v11_0_hpd_init()
373 			WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v11_0_hpd_init()
377 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v11_0_hpd_init()
379 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v11_0_hpd_init()
381 		tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v11_0_hpd_init()
388 		WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v11_0_hpd_init()
390 		dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);  in dce_v11_0_hpd_init()
391 		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);  in dce_v11_0_hpd_init()
397  * dce_v11_0_hpd_fini - hpd tear down callback.
401  * Tear down the hpd pins used by the card (evergreen+).
402  * Disable the hpd interrupts.
415 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v11_0_hpd_fini()
418 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v11_0_hpd_fini()
420 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v11_0_hpd_fini()
422 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);  in dce_v11_0_hpd_fini()
2906 	/* HPD hotplug */  in dce_v11_0_sw_init()
3011 	/* initialize hpd */  in dce_v11_0_hw_init()
3176 					unsigned hpd,  in dce_v11_0_set_hpd_irq_state()  argument
3181 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v11_0_set_hpd_irq_state()
3182 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v11_0_set_hpd_irq_state()
3188 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_set_hpd_irq_state()
3190 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_set_hpd_irq_state()
3193 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_set_hpd_irq_state()
3195 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_set_hpd_irq_state()
3329 				  int hpd)  in dce_v11_0_hpd_int_ack()  argument
3333 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v11_0_hpd_int_ack()
3334 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v11_0_hpd_int_ack()
3338 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v11_0_hpd_int_ack()
3340 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v11_0_hpd_int_ack()
3417 	unsigned hpd;  in dce_v11_0_hpd_irq()  local
3424 	hpd = entry->src_data[0];  in dce_v11_0_hpd_irq()
3425 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);  in dce_v11_0_hpd_irq()
3426 	mask = interrupt_status_offsets[hpd].hpd;  in dce_v11_0_hpd_irq()
3429 		dce_v11_0_hpd_int_ack(adev, hpd);  in dce_v11_0_hpd_irq()
3431 		DRM_DEBUG("IH: HPD%d\n", hpd + 1);  in dce_v11_0_hpd_irq()