Lines Matching refs:crtc
195 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) in dce_v10_0_vblank_get_counter() argument
197 if (crtc >= adev->mode_info.num_crtc) in dce_v10_0_vblank_get_counter()
200 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in dce_v10_0_vblank_get_counter()
257 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, in dce_v10_0_crtc_get_scanoutpos() argument
260 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) in dce_v10_0_crtc_get_scanoutpos()
263 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v10_0_crtc_get_scanoutpos()
264 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v10_0_crtc_get_scanoutpos()
506 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v10_0_program_fmt()
1540 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v10_0_audio_set_dto()
1586 if (encoder->crtc) { in dce_v10_0_afmt_setmode()
1587 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v10_0_afmt_setmode()
1816 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable) in dce_v10_0_vga_enable() argument
1818 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_vga_enable()
1819 struct drm_device *dev = crtc->dev; in dce_v10_0_vga_enable()
1830 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable) in dce_v10_0_grph_enable() argument
1832 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_grph_enable()
1833 struct drm_device *dev = crtc->dev; in dce_v10_0_grph_enable()
1842 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, in dce_v10_0_crtc_do_set_base() argument
1846 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_do_set_base()
1847 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_do_set_base()
1861 if (!atomic && !crtc->primary->fb) { in dce_v10_0_crtc_do_set_base()
1869 target_fb = crtc->primary->fb; in dce_v10_0_crtc_do_set_base()
2010 dce_v10_0_vga_enable(crtc, false); in dce_v10_0_crtc_do_set_base()
2056 dce_v10_0_grph_enable(crtc, true); in dce_v10_0_crtc_do_set_base()
2065 viewport_w = crtc->mode.hdisplay; in dce_v10_0_crtc_do_set_base()
2066 viewport_h = (crtc->mode.vdisplay + 1) & ~1; in dce_v10_0_crtc_do_set_base()
2073 if (!atomic && fb && fb != crtc->primary->fb) { in dce_v10_0_crtc_do_set_base()
2088 static void dce_v10_0_set_interleave(struct drm_crtc *crtc, in dce_v10_0_set_interleave() argument
2091 struct drm_device *dev = crtc->dev; in dce_v10_0_set_interleave()
2093 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_set_interleave()
2104 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc) in dce_v10_0_crtc_load_lut() argument
2106 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_load_lut()
2107 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_load_lut()
2147 r = crtc->gamma_store; in dce_v10_0_crtc_load_lut()
2148 g = r + crtc->gamma_size; in dce_v10_0_crtc_load_lut()
2149 b = g + crtc->gamma_size; in dce_v10_0_crtc_load_lut()
2239 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc) in dce_v10_0_pick_pll() argument
2241 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_pick_pll()
2242 struct drm_device *dev = crtc->dev; in dce_v10_0_pick_pll()
2253 pll = amdgpu_pll_get_shared_dp_ppll(crtc); in dce_v10_0_pick_pll()
2259 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); in dce_v10_0_pick_pll()
2265 pll_in_use = amdgpu_pll_get_use_mask(crtc); in dce_v10_0_pick_pll()
2276 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock) in dce_v10_0_lock_cursor() argument
2278 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v10_0_lock_cursor()
2279 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_lock_cursor()
2290 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc) in dce_v10_0_hide_cursor() argument
2292 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_hide_cursor()
2293 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v10_0_hide_cursor()
2301 static void dce_v10_0_show_cursor(struct drm_crtc *crtc) in dce_v10_0_show_cursor() argument
2303 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_show_cursor()
2304 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v10_0_show_cursor()
2318 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc, in dce_v10_0_cursor_move_locked() argument
2321 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_cursor_move_locked()
2322 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v10_0_cursor_move_locked()
2329 x += crtc->x; in dce_v10_0_cursor_move_locked()
2330 y += crtc->y; in dce_v10_0_cursor_move_locked()
2331 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); in dce_v10_0_cursor_move_locked()
2350 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc, in dce_v10_0_crtc_cursor_move() argument
2355 dce_v10_0_lock_cursor(crtc, true); in dce_v10_0_crtc_cursor_move()
2356 ret = dce_v10_0_cursor_move_locked(crtc, x, y); in dce_v10_0_crtc_cursor_move()
2357 dce_v10_0_lock_cursor(crtc, false); in dce_v10_0_crtc_cursor_move()
2362 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, in dce_v10_0_crtc_cursor_set2() argument
2370 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_cursor_set2()
2377 dce_v10_0_hide_cursor(crtc); in dce_v10_0_crtc_cursor_set2()
2410 dce_v10_0_lock_cursor(crtc, true); in dce_v10_0_crtc_cursor_set2()
2421 dce_v10_0_cursor_move_locked(crtc, x, y); in dce_v10_0_crtc_cursor_set2()
2429 dce_v10_0_show_cursor(crtc); in dce_v10_0_crtc_cursor_set2()
2430 dce_v10_0_lock_cursor(crtc, false); in dce_v10_0_crtc_cursor_set2()
2447 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc) in dce_v10_0_cursor_reset() argument
2449 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_cursor_reset()
2452 dce_v10_0_lock_cursor(crtc, true); in dce_v10_0_cursor_reset()
2454 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, in dce_v10_0_cursor_reset()
2457 dce_v10_0_show_cursor(crtc); in dce_v10_0_cursor_reset()
2459 dce_v10_0_lock_cursor(crtc, false); in dce_v10_0_cursor_reset()
2463 static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, in dce_v10_0_crtc_gamma_set() argument
2467 dce_v10_0_crtc_load_lut(crtc); in dce_v10_0_crtc_gamma_set()
2472 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc) in dce_v10_0_crtc_destroy() argument
2474 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_destroy()
2476 drm_crtc_cleanup(crtc); in dce_v10_0_crtc_destroy()
2493 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode) in dce_v10_0_crtc_dpms() argument
2495 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_dpms()
2497 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_dpms()
2503 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); in dce_v10_0_crtc_dpms()
2504 dce_v10_0_vga_enable(crtc, true); in dce_v10_0_crtc_dpms()
2505 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); in dce_v10_0_crtc_dpms()
2506 dce_v10_0_vga_enable(crtc, false); in dce_v10_0_crtc_dpms()
2512 drm_crtc_vblank_on(crtc); in dce_v10_0_crtc_dpms()
2513 dce_v10_0_crtc_load_lut(crtc); in dce_v10_0_crtc_dpms()
2518 drm_crtc_vblank_off(crtc); in dce_v10_0_crtc_dpms()
2520 dce_v10_0_vga_enable(crtc, true); in dce_v10_0_crtc_dpms()
2521 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); in dce_v10_0_crtc_dpms()
2522 dce_v10_0_vga_enable(crtc, false); in dce_v10_0_crtc_dpms()
2524 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); in dce_v10_0_crtc_dpms()
2532 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc) in dce_v10_0_crtc_prepare() argument
2535 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); in dce_v10_0_crtc_prepare()
2536 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); in dce_v10_0_crtc_prepare()
2537 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); in dce_v10_0_crtc_prepare()
2540 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc) in dce_v10_0_crtc_commit() argument
2542 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); in dce_v10_0_crtc_commit()
2543 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); in dce_v10_0_crtc_commit()
2546 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc) in dce_v10_0_crtc_disable() argument
2548 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_disable()
2549 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_disable()
2554 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); in dce_v10_0_crtc_disable()
2555 if (crtc->primary->fb) { in dce_v10_0_crtc_disable()
2559 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); in dce_v10_0_crtc_disable()
2569 dce_v10_0_grph_enable(crtc, false); in dce_v10_0_crtc_disable()
2571 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); in dce_v10_0_crtc_disable()
2590 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, in dce_v10_0_crtc_disable()
2603 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc, in dce_v10_0_crtc_mode_set() argument
2608 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_mode_set()
2613 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); in dce_v10_0_crtc_mode_set()
2614 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); in dce_v10_0_crtc_mode_set()
2615 dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); in dce_v10_0_crtc_mode_set()
2616 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); in dce_v10_0_crtc_mode_set()
2617 amdgpu_atombios_crtc_scaler_setup(crtc); in dce_v10_0_crtc_mode_set()
2618 dce_v10_0_cursor_reset(crtc); in dce_v10_0_crtc_mode_set()
2625 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc, in dce_v10_0_crtc_mode_fixup() argument
2629 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_mode_fixup()
2630 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_mode_fixup()
2635 if (encoder->crtc == crtc) { in dce_v10_0_crtc_mode_fixup()
2646 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) in dce_v10_0_crtc_mode_fixup()
2648 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) in dce_v10_0_crtc_mode_fixup()
2651 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc); in dce_v10_0_crtc_mode_fixup()
2660 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, in dce_v10_0_crtc_set_base() argument
2663 return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); in dce_v10_0_crtc_set_base()
2666 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc, in dce_v10_0_crtc_set_base_atomic() argument
2670 return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1); in dce_v10_0_crtc_set_base_atomic()
2986 int crtc, in dce_v10_0_set_crtc_vblank_interrupt_state() argument
2991 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_set_crtc_vblank_interrupt_state()
2992 DRM_DEBUG("invalid crtc %d\n", crtc); in dce_v10_0_set_crtc_vblank_interrupt_state()
2998 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v10_0_set_crtc_vblank_interrupt_state()
3001 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v10_0_set_crtc_vblank_interrupt_state()
3004 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v10_0_set_crtc_vblank_interrupt_state()
3007 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v10_0_set_crtc_vblank_interrupt_state()
3015 int crtc, in dce_v10_0_set_crtc_vline_interrupt_state() argument
3020 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_set_crtc_vline_interrupt_state()
3021 DRM_DEBUG("invalid crtc %d\n", crtc); in dce_v10_0_set_crtc_vline_interrupt_state()
3027 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v10_0_set_crtc_vline_interrupt_state()
3030 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v10_0_set_crtc_vline_interrupt_state()
3033 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v10_0_set_crtc_vline_interrupt_state()
3036 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v10_0_set_crtc_vline_interrupt_state()
3213 int crtc) in dce_v10_0_crtc_vblank_int_ack() argument
3217 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_crtc_vblank_int_ack()
3218 DRM_DEBUG("invalid crtc %d\n", crtc); in dce_v10_0_crtc_vblank_int_ack()
3222 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); in dce_v10_0_crtc_vblank_int_ack()
3224 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); in dce_v10_0_crtc_vblank_int_ack()
3228 int crtc) in dce_v10_0_crtc_vline_int_ack() argument
3232 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_crtc_vline_int_ack()
3233 DRM_DEBUG("invalid crtc %d\n", crtc); in dce_v10_0_crtc_vline_int_ack()
3237 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); in dce_v10_0_crtc_vline_int_ack()
3239 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); in dce_v10_0_crtc_vline_int_ack()
3246 unsigned crtc = entry->src_id - 1; in dce_v10_0_crtc_irq() local
3247 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v10_0_crtc_irq()
3248 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, crtc); in dce_v10_0_crtc_irq()
3252 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v10_0_crtc_irq()
3253 dce_v10_0_crtc_vblank_int_ack(adev, crtc); in dce_v10_0_crtc_irq()
3258 drm_handle_vblank(adev_to_drm(adev), crtc); in dce_v10_0_crtc_irq()
3260 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); in dce_v10_0_crtc_irq()
3264 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v10_0_crtc_irq()
3265 dce_v10_0_crtc_vline_int_ack(adev, crtc); in dce_v10_0_crtc_irq()
3269 DRM_DEBUG("IH: D%d vline\n", crtc + 1); in dce_v10_0_crtc_irq()
3348 dce_v10_0_set_interleave(encoder->crtc, mode); in dce_v10_0_encoder_mode_set()