Lines Matching defs:amdgpu_crtc

368 struct amdgpu_crtc {  struct
369 	struct drm_crtc base;
370 	int crtc_id;
371 	bool enabled;
372 	bool can_tile;
373 	uint32_t crtc_offset;
374 	struct drm_gem_object *cursor_bo;
375 	uint64_t cursor_addr;
376 	int cursor_x;
377 	int cursor_y;
378 	int cursor_hot_x;
379 	int cursor_hot_y;
380 	int cursor_width;
381 	int cursor_height;
382 	int max_cursor_width;
383 	int max_cursor_height;
384 	enum amdgpu_rmx_type rmx_type;
385 	u8 h_border;
386 	u8 v_border;
387 	fixed20_12 vsc;
388 	fixed20_12 hsc;
389 	struct drm_display_mode native_mode;
390 	u32 pll_id;
392 	struct amdgpu_flip_work *pflip_works;
393 	enum amdgpu_flip_status pflip_status;
394 	int deferred_flip_completion;
396 	struct dm_irq_params dm_irq_params;
398 	struct amdgpu_atom_ss ss;
399 	bool ss_enabled;
400 	u32 adjusted_clock;
401 	int bpc;
402 	u32 pll_reference_div;
403 	u32 pll_post_div;
404 	u32 pll_flags;
405 	struct drm_encoder *encoder;
406 	struct drm_connector *connector;
408 	u32 line_time;
409 	u32 wm_low;
410 	u32 wm_high;
411 	u32 lb_vblank_lead_lines;
412 	struct drm_display_mode hw_mode;
414 	struct hrtimer vblank_timer;
415 	enum amdgpu_interrupt_state vsync_timer_enabled;
417 	int otg_inst;
418 	struct drm_pending_vblank_event *event;