347 struct amdgpu_gfx {  struct
349 	struct amdgpu_gfx_config	config;  argument
350 	struct amdgpu_rlc		rlc;
351 	struct amdgpu_pfp		pfp;
352 	struct amdgpu_ce		ce;
353 	struct amdgpu_me		me;
354 	struct amdgpu_mec		mec;
355 	struct amdgpu_mec_bitmap	mec_bitmap[AMDGPU_MAX_GC_INSTANCES];
356 	struct amdgpu_kiq		kiq[AMDGPU_MAX_GC_INSTANCES];
357 	struct amdgpu_imu		imu;
358 	bool				rs64_enable; /* firmware format */
359 	const struct firmware		*me_fw;	/* ME firmware */
360 	uint32_t			me_fw_version;
361 	const struct firmware		*pfp_fw; /* PFP firmware */
362 	uint32_t			pfp_fw_version;
363 	const struct firmware		*ce_fw;	/* CE firmware */
364 	uint32_t			ce_fw_version;
365 	const struct firmware		*rlc_fw; /* RLC firmware */
366 	uint32_t			rlc_fw_version;
367 	const struct firmware		*mec_fw; /* MEC firmware */
368 	uint32_t			mec_fw_version;
369 	const struct firmware		*mec2_fw; /* MEC2 firmware */
370 	uint32_t			mec2_fw_version;
371 	const struct firmware		*imu_fw; /* IMU firmware */
372 	uint32_t			imu_fw_version;
373 	uint32_t			me_feature_version;
374 	uint32_t			ce_feature_version;
375 	uint32_t			pfp_feature_version;
376 	uint32_t			rlc_feature_version;
377 	uint32_t			rlc_srlc_fw_version;
378 	uint32_t			rlc_srlc_feature_version;
379 	uint32_t			rlc_srlg_fw_version;
380 	uint32_t			rlc_srlg_feature_version;
381 	uint32_t			rlc_srls_fw_version;
382 	uint32_t			rlc_srls_feature_version;
383 	uint32_t			rlcp_ucode_version;
384 	uint32_t			rlcp_ucode_feature_version;
385 	uint32_t			rlcv_ucode_version;
409 	const struct amdgpu_gfx_funcs	*funcs;  argument
429 	struct amdgpu_gfx_ras		*ras;  argument
444 struct amdgpu_gfx_ras_reg_entry {  argument