Lines Matching +full:ati +full:- +full:target
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
51 * amdgpu_display_hotplug_work_func - work handler for display hotplug event
71 struct drm_mode_config *mode_config = &dev->mode_config; in amdgpu_display_hotplug_work_func()
75 mutex_lock(&mode_config->mutex); in amdgpu_display_hotplug_work_func()
80 mutex_unlock(&mode_config->mutex); in amdgpu_display_hotplug_work_func()
97 schedule_work(&work->flip_work.work); in amdgpu_display_flip_callback()
110 if (!dma_fence_add_callback(fence, &work->cb, in amdgpu_display_flip_handle_fence()
124 struct amdgpu_device *adev = work->adev; in amdgpu_display_flip_work_func()
125 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id]; in amdgpu_display_flip_work_func()
127 struct drm_crtc *crtc = &amdgpu_crtc->base; in amdgpu_display_flip_work_func()
132 for (i = 0; i < work->shared_count; ++i) in amdgpu_display_flip_work_func()
133 if (amdgpu_display_flip_handle_fence(work, &work->shared[i])) in amdgpu_display_flip_work_func()
139 if (amdgpu_crtc->enabled && in amdgpu_display_flip_work_func()
140 (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0, in amdgpu_display_flip_work_func()
142 &crtc->hwmode) in amdgpu_display_flip_work_func()
145 (int)(work->target_vblank - in amdgpu_display_flip_work_func()
147 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000)); in amdgpu_display_flip_work_func()
152 spin_lock_irqsave(&crtc->dev->event_lock, flags); in amdgpu_display_flip_work_func()
155 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); in amdgpu_display_flip_work_func()
158 amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED; in amdgpu_display_flip_work_func()
159 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); in amdgpu_display_flip_work_func()
164 amdgpu_crtc->crtc_id, amdgpu_crtc, work); in amdgpu_display_flip_work_func()
178 r = amdgpu_bo_reserve(work->old_abo, true); in amdgpu_display_unpin_work_func()
180 amdgpu_bo_unpin(work->old_abo); in amdgpu_display_unpin_work_func()
181 amdgpu_bo_unreserve(work->old_abo); in amdgpu_display_unpin_work_func()
185 amdgpu_bo_unref(&work->old_abo); in amdgpu_display_unpin_work_func()
186 kfree(work->shared); in amdgpu_display_unpin_work_func()
193 uint32_t page_flip_flags, uint32_t target, in amdgpu_display_crtc_page_flip_target() argument
196 struct drm_device *dev = crtc->dev; in amdgpu_display_crtc_page_flip_target()
208 return -ENOMEM; in amdgpu_display_crtc_page_flip_target()
210 INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func); in amdgpu_display_crtc_page_flip_target()
211 INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func); in amdgpu_display_crtc_page_flip_target()
213 work->event = event; in amdgpu_display_crtc_page_flip_target()
214 work->adev = adev; in amdgpu_display_crtc_page_flip_target()
215 work->crtc_id = amdgpu_crtc->crtc_id; in amdgpu_display_crtc_page_flip_target()
216 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; in amdgpu_display_crtc_page_flip_target()
219 obj = crtc->primary->fb->obj[0]; in amdgpu_display_crtc_page_flip_target()
222 work->old_abo = gem_to_amdgpu_bo(obj); in amdgpu_display_crtc_page_flip_target()
223 amdgpu_bo_ref(work->old_abo); in amdgpu_display_crtc_page_flip_target()
225 obj = fb->obj[0]; in amdgpu_display_crtc_page_flip_target()
235 if (!adev->enable_virtual_display) { in amdgpu_display_crtc_page_flip_target()
237 amdgpu_display_supported_domains(adev, new_abo->flags)); in amdgpu_display_crtc_page_flip_target()
244 r = amdgpu_ttm_alloc_gart(&new_abo->tbo); in amdgpu_display_crtc_page_flip_target()
250 r = dma_resv_get_fences(new_abo->tbo.base.resv, DMA_RESV_USAGE_WRITE, in amdgpu_display_crtc_page_flip_target()
251 &work->shared_count, in amdgpu_display_crtc_page_flip_target()
252 &work->shared); in amdgpu_display_crtc_page_flip_target()
261 if (!adev->enable_virtual_display) in amdgpu_display_crtc_page_flip_target()
262 work->base = amdgpu_bo_gpu_offset(new_abo); in amdgpu_display_crtc_page_flip_target()
263 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + in amdgpu_display_crtc_page_flip_target()
267 spin_lock_irqsave(&crtc->dev->event_lock, flags); in amdgpu_display_crtc_page_flip_target()
268 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { in amdgpu_display_crtc_page_flip_target()
270 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); in amdgpu_display_crtc_page_flip_target()
271 r = -EBUSY; in amdgpu_display_crtc_page_flip_target()
275 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; in amdgpu_display_crtc_page_flip_target()
276 amdgpu_crtc->pflip_works = work; in amdgpu_display_crtc_page_flip_target()
280 amdgpu_crtc->crtc_id, amdgpu_crtc, work); in amdgpu_display_crtc_page_flip_target()
282 crtc->primary->fb = fb; in amdgpu_display_crtc_page_flip_target()
283 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); in amdgpu_display_crtc_page_flip_target()
284 amdgpu_display_flip_work_func(&work->flip_work.work); in amdgpu_display_crtc_page_flip_target()
293 if (!adev->enable_virtual_display) in amdgpu_display_crtc_page_flip_target()
300 amdgpu_bo_unref(&work->old_abo); in amdgpu_display_crtc_page_flip_target()
301 for (i = 0; i < work->shared_count; ++i) in amdgpu_display_crtc_page_flip_target()
302 dma_fence_put(work->shared[i]); in amdgpu_display_crtc_page_flip_target()
303 kfree(work->shared); in amdgpu_display_crtc_page_flip_target()
318 if (!set || !set->crtc) in amdgpu_display_crtc_set_config()
319 return -EINVAL; in amdgpu_display_crtc_set_config()
321 dev = set->crtc->dev; in amdgpu_display_crtc_set_config()
323 ret = pm_runtime_get_sync(dev->dev); in amdgpu_display_crtc_set_config()
329 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) in amdgpu_display_crtc_set_config()
330 if (crtc->enabled) in amdgpu_display_crtc_set_config()
333 pm_runtime_mark_last_busy(dev->dev); in amdgpu_display_crtc_set_config()
339 if (active && !adev->have_disp_power_ref) { in amdgpu_display_crtc_set_config()
340 adev->have_disp_power_ref = true; in amdgpu_display_crtc_set_config()
346 if (!active && adev->have_disp_power_ref) in amdgpu_display_crtc_set_config()
347 adev->have_disp_power_ref = false; in amdgpu_display_crtc_set_config()
350 pm_runtime_put_autosuspend(dev->dev); in amdgpu_display_crtc_set_config()
422 DRM_INFO(" %s\n", connector->name); in amdgpu_display_print_display_setup()
423 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) in amdgpu_display_print_display_setup()
424 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); in amdgpu_display_print_display_setup()
425 if (amdgpu_connector->ddc_bus) { in amdgpu_display_print_display_setup()
427 amdgpu_connector->ddc_bus->rec.mask_clk_reg, in amdgpu_display_print_display_setup()
428 amdgpu_connector->ddc_bus->rec.mask_data_reg, in amdgpu_display_print_display_setup()
429 amdgpu_connector->ddc_bus->rec.a_clk_reg, in amdgpu_display_print_display_setup()
430 amdgpu_connector->ddc_bus->rec.a_data_reg, in amdgpu_display_print_display_setup()
431 amdgpu_connector->ddc_bus->rec.en_clk_reg, in amdgpu_display_print_display_setup()
432 amdgpu_connector->ddc_bus->rec.en_data_reg, in amdgpu_display_print_display_setup()
433 amdgpu_connector->ddc_bus->rec.y_clk_reg, in amdgpu_display_print_display_setup()
434 amdgpu_connector->ddc_bus->rec.y_data_reg); in amdgpu_display_print_display_setup()
435 if (amdgpu_connector->router.ddc_valid) in amdgpu_display_print_display_setup()
437 amdgpu_connector->router.ddc_mux_control_pin, in amdgpu_display_print_display_setup()
438 amdgpu_connector->router.ddc_mux_state); in amdgpu_display_print_display_setup()
439 if (amdgpu_connector->router.cd_valid) in amdgpu_display_print_display_setup()
441 amdgpu_connector->router.cd_mux_control_pin, in amdgpu_display_print_display_setup()
442 amdgpu_connector->router.cd_mux_state); in amdgpu_display_print_display_setup()
444 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || in amdgpu_display_print_display_setup()
445 connector->connector_type == DRM_MODE_CONNECTOR_DVII || in amdgpu_display_print_display_setup()
446 connector->connector_type == DRM_MODE_CONNECTOR_DVID || in amdgpu_display_print_display_setup()
447 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || in amdgpu_display_print_display_setup()
448 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || in amdgpu_display_print_display_setup()
449 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) in amdgpu_display_print_display_setup()
450 …DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); in amdgpu_display_print_display_setup()
453 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in amdgpu_display_print_display_setup()
455 devices = amdgpu_encoder->devices & amdgpu_connector->devices; in amdgpu_display_print_display_setup()
458 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); in amdgpu_display_print_display_setup()
460 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); in amdgpu_display_print_display_setup()
462 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); in amdgpu_display_print_display_setup()
464 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); in amdgpu_display_print_display_setup()
466 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); in amdgpu_display_print_display_setup()
468 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); in amdgpu_display_print_display_setup()
470 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); in amdgpu_display_print_display_setup()
472 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); in amdgpu_display_print_display_setup()
474 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); in amdgpu_display_print_display_setup()
476 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); in amdgpu_display_print_display_setup()
478 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); in amdgpu_display_print_display_setup()
508 if (amdgpu_connector->router.ddc_valid) in amdgpu_display_ddc_probe()
512 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); in amdgpu_display_ddc_probe()
514 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); in amdgpu_display_ddc_probe()
540 return -ENOSYS; in amdgpu_dirtyfb()
573 adev->dc_enabled && in amdgpu_display_supported_domains()
574 adev->mode_info.gpu_vm_support) in amdgpu_display_supported_domains()
689 /* Don't show error message when returning -ERESTARTSYS */ in extract_render_dcc_offset()
690 if (r != -ERESTARTSYS) in extract_render_dcc_offset()
706 return -EINVAL; in extract_render_dcc_offset()
708 if (adev->family >= AMDGPU_FAMILY_NV) { in extract_render_dcc_offset()
723 struct amdgpu_device *adev = drm_to_adev(afb->base.dev); in convert_tiling_flags_to_modifier()
728 num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; in convert_tiling_flags_to_modifier()
729 num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes; in convert_tiling_flags_to_modifier()
731 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) { in convert_tiling_flags_to_modifier()
734 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE); in convert_tiling_flags_to_modifier()
743 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B); in convert_tiling_flags_to_modifier()
763 return -EINVAL; in convert_tiling_flags_to_modifier()
766 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) in convert_tiling_flags_to_modifier()
768 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) in convert_tiling_flags_to_modifier()
770 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0)) in convert_tiling_flags_to_modifier()
777 return -EINVAL; in convert_tiling_flags_to_modifier()
779 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) { in convert_tiling_flags_to_modifier()
785 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) { in convert_tiling_flags_to_modifier()
786 if (!has_xor && afb->base.format->cpp[0] != 4) in convert_tiling_flags_to_modifier()
797 return -EINVAL; in convert_tiling_flags_to_modifier()
802 pipe_xor_bits = min(block_size_bits - 8, pipes); in convert_tiling_flags_to_modifier()
803 packers = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs); in convert_tiling_flags_to_modifier()
806 pipe_xor_bits = min(block_size_bits - 8, pipes); in convert_tiling_flags_to_modifier()
807 packers = min(block_size_bits - 8 - pipe_xor_bits, in convert_tiling_flags_to_modifier()
808 ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs)); in convert_tiling_flags_to_modifier()
811 pipe_xor_bits = min(block_size_bits - 8, pipes); in convert_tiling_flags_to_modifier()
814 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + in convert_tiling_flags_to_modifier()
815 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se); in convert_tiling_flags_to_modifier()
816 pipe_xor_bits = min(block_size_bits - 8, pipes + in convert_tiling_flags_to_modifier()
817 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); in convert_tiling_flags_to_modifier()
818 bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits, in convert_tiling_flags_to_modifier()
819 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); in convert_tiling_flags_to_modifier()
825 AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) | in convert_tiling_flags_to_modifier()
832 bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0; in convert_tiling_flags_to_modifier()
838 bool dcc_constant_encode = (adev->asic_type > CHIP_RAVEN || in convert_tiling_flags_to_modifier()
839 (adev->asic_type == CHIP_RAVEN && in convert_tiling_flags_to_modifier()
840 adev->external_rev_id >= 0x81)) && in convert_tiling_flags_to_modifier()
841 adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0); in convert_tiling_flags_to_modifier()
853 afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0]; in convert_tiling_flags_to_modifier()
854 afb->base.pitches[1] = in convert_tiling_flags_to_modifier()
855 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1; in convert_tiling_flags_to_modifier()
865 if (extract_render_dcc_offset(adev, afb->base.obj[0], in convert_tiling_flags_to_modifier()
868 render_dcc_offset != afb->base.offsets[1] && in convert_tiling_flags_to_modifier()
873 afb->base.offsets[2] = render_dcc_offset; in convert_tiling_flags_to_modifier()
875 if (adev->family >= AMDGPU_FAMILY_NV) { in convert_tiling_flags_to_modifier()
878 if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) && in convert_tiling_flags_to_modifier()
889 dcc_block_bits -= ilog2(afb->base.format->cpp[0]); in convert_tiling_flags_to_modifier()
890 afb->base.pitches[2] = ALIGN(afb->base.width, in convert_tiling_flags_to_modifier()
893 format_info = amdgpu_lookup_format_info(afb->base.format->format, in convert_tiling_flags_to_modifier()
896 return -EINVAL; in convert_tiling_flags_to_modifier()
898 afb->base.format = format_info; in convert_tiling_flags_to_modifier()
902 afb->base.modifier = modifier; in convert_tiling_flags_to_modifier()
903 afb->base.flags |= DRM_MODE_FB_MODIFIERS; in convert_tiling_flags_to_modifier()
912 if (AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) == 1) /* LINEAR_ALIGNED */ in check_tiling_flags_gfx6()
915 micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE); in check_tiling_flags_gfx6()
921 drm_dbg_kms(afb->base.dev, in check_tiling_flags_gfx6()
924 return -EINVAL; in check_tiling_flags_gfx6()
932 unsigned int pixel_log2 = block_log2 - cpp_log2; in get_block_dimensions()
934 unsigned int height_log2 = pixel_log2 - width_log2; in get_block_dimensions()
975 unsigned int width = rfb->base.width / in amdgpu_display_verify_plane()
976 ((plane && plane < format->num_planes) ? format->hsub : 1); in amdgpu_display_verify_plane()
977 unsigned int height = rfb->base.height / in amdgpu_display_verify_plane()
978 ((plane && plane < format->num_planes) ? format->vsub : 1); in amdgpu_display_verify_plane()
979 unsigned int cpp = plane < format->num_planes ? format->cpp[plane] : 1; in amdgpu_display_verify_plane()
985 if (rfb->base.pitches[plane] % block_pitch) { in amdgpu_display_verify_plane()
986 drm_dbg_kms(rfb->base.dev, in amdgpu_display_verify_plane()
988 rfb->base.pitches[plane], plane, block_pitch); in amdgpu_display_verify_plane()
989 return -EINVAL; in amdgpu_display_verify_plane()
991 if (rfb->base.pitches[plane] < min_pitch) { in amdgpu_display_verify_plane()
992 drm_dbg_kms(rfb->base.dev, in amdgpu_display_verify_plane()
994 rfb->base.pitches[plane], plane, min_pitch); in amdgpu_display_verify_plane()
995 return -EINVAL; in amdgpu_display_verify_plane()
999 if (rfb->base.offsets[plane] % block_size) { in amdgpu_display_verify_plane()
1000 drm_dbg_kms(rfb->base.dev, in amdgpu_display_verify_plane()
1002 rfb->base.offsets[plane], plane, block_size); in amdgpu_display_verify_plane()
1003 return -EINVAL; in amdgpu_display_verify_plane()
1006 size = rfb->base.offsets[plane] + in amdgpu_display_verify_plane()
1007 (uint64_t)rfb->base.pitches[plane] / block_pitch * in amdgpu_display_verify_plane()
1010 if (rfb->base.obj[0]->size < size) { in amdgpu_display_verify_plane()
1011 drm_dbg_kms(rfb->base.dev, in amdgpu_display_verify_plane()
1013 rfb->base.obj[0]->size, size, plane); in amdgpu_display_verify_plane()
1014 return -EINVAL; in amdgpu_display_verify_plane()
1023 const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format); in amdgpu_display_verify_sizes()
1024 uint64_t modifier = rfb->base.modifier; in amdgpu_display_verify_sizes()
1028 if (rfb->base.dev->mode_config.fb_modifiers_not_supported) in amdgpu_display_verify_sizes()
1031 for (i = 0; i < format_info->num_planes; ++i) { in amdgpu_display_verify_sizes()
1033 block_width = 256 / format_info->cpp[i]; in amdgpu_display_verify_sizes()
1053 drm_dbg_kms(rfb->base.dev, in amdgpu_display_verify_sizes()
1055 return -EINVAL; in amdgpu_display_verify_sizes()
1058 get_block_dimensions(block_size_log2, format_info->cpp[i], in amdgpu_display_verify_sizes()
1080 drm_dbg_kms(rfb->base.dev, in amdgpu_display_verify_sizes()
1082 return -EINVAL; in amdgpu_display_verify_sizes()
1085 get_block_dimensions(block_size_log2, format_info->cpp[i], in amdgpu_display_verify_sizes()
1099 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0], in amdgpu_display_verify_sizes()
1114 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0], in amdgpu_display_verify_sizes()
1137 rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); in amdgpu_display_get_fb_info()
1141 /* Don't show error message when returning -ERESTARTSYS */ in amdgpu_display_get_fb_info()
1142 if (r != -ERESTARTSYS) in amdgpu_display_get_fb_info()
1166 rfb->base.obj[0] = obj; in amdgpu_display_gem_fb_verify_and_init()
1167 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); in amdgpu_display_gem_fb_verify_and_init()
1169 if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, in amdgpu_display_gem_fb_verify_and_init()
1170 mode_cmd->modifier[0])) { in amdgpu_display_gem_fb_verify_and_init()
1173 &mode_cmd->pixel_format, mode_cmd->modifier[0]); in amdgpu_display_gem_fb_verify_and_init()
1175 ret = -EINVAL; in amdgpu_display_gem_fb_verify_and_init()
1184 ret = drm_framebuffer_init(dev, &rfb->base, in amdgpu_display_gem_fb_verify_and_init()
1187 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); in amdgpu_display_gem_fb_verify_and_init()
1195 rfb->base.obj[0] = NULL; in amdgpu_display_gem_fb_verify_and_init()
1211 for (i = 1; i < rfb->base.format->num_planes; ++i) { in amdgpu_display_framebuffer_init()
1212 if (mode_cmd->handles[i] != mode_cmd->handles[0]) { in amdgpu_display_framebuffer_init()
1214 i, mode_cmd->handles[0], mode_cmd->handles[i]); in amdgpu_display_framebuffer_init()
1215 ret = -EINVAL; in amdgpu_display_framebuffer_init()
1220 ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface); in amdgpu_display_framebuffer_init()
1224 if (dev->mode_config.fb_modifiers_not_supported && !adev->enable_virtual_display) { in amdgpu_display_framebuffer_init()
1225 drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI, in amdgpu_display_framebuffer_init()
1232 if (!dev->mode_config.fb_modifiers_not_supported && in amdgpu_display_framebuffer_init()
1233 !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) { in amdgpu_display_framebuffer_init()
1237 rfb->tiling_flags); in amdgpu_display_framebuffer_init()
1246 for (i = 0; i < rfb->base.format->num_planes; ++i) { in amdgpu_display_framebuffer_init()
1247 drm_gem_object_get(rfb->base.obj[0]); in amdgpu_display_framebuffer_init()
1248 rfb->base.obj[i] = rfb->base.obj[0]; in amdgpu_display_framebuffer_init()
1265 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); in amdgpu_display_user_framebuffer_create()
1269 mode_cmd->handles[0]); in amdgpu_display_user_framebuffer_create()
1271 return ERR_PTR(-ENOENT); in amdgpu_display_user_framebuffer_create()
1274 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ in amdgpu_display_user_framebuffer_create()
1276 domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags); in amdgpu_display_user_framebuffer_create()
1277 if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) { in amdgpu_display_user_framebuffer_create()
1280 return ERR_PTR(-EINVAL); in amdgpu_display_user_framebuffer_create()
1286 return ERR_PTR(-ENOMEM); in amdgpu_display_user_framebuffer_create()
1298 return &amdgpu_fb->base; in amdgpu_display_user_framebuffer_create()
1327 adev->mode_info.coherent_mode_property = in amdgpu_display_modeset_create_props()
1329 if (!adev->mode_info.coherent_mode_property) in amdgpu_display_modeset_create_props()
1330 return -ENOMEM; in amdgpu_display_modeset_create_props()
1332 adev->mode_info.load_detect_property = in amdgpu_display_modeset_create_props()
1334 if (!adev->mode_info.load_detect_property) in amdgpu_display_modeset_create_props()
1335 return -ENOMEM; in amdgpu_display_modeset_create_props()
1340 adev->mode_info.underscan_property = in amdgpu_display_modeset_create_props()
1345 adev->mode_info.underscan_hborder_property = in amdgpu_display_modeset_create_props()
1348 if (!adev->mode_info.underscan_hborder_property) in amdgpu_display_modeset_create_props()
1349 return -ENOMEM; in amdgpu_display_modeset_create_props()
1351 adev->mode_info.underscan_vborder_property = in amdgpu_display_modeset_create_props()
1354 if (!adev->mode_info.underscan_vborder_property) in amdgpu_display_modeset_create_props()
1355 return -ENOMEM; in amdgpu_display_modeset_create_props()
1358 adev->mode_info.audio_property = in amdgpu_display_modeset_create_props()
1364 adev->mode_info.dither_property = in amdgpu_display_modeset_create_props()
1369 if (adev->dc_enabled) { in amdgpu_display_modeset_create_props()
1370 adev->mode_info.abm_level_property = in amdgpu_display_modeset_create_props()
1373 if (!adev->mode_info.abm_level_property) in amdgpu_display_modeset_create_props()
1374 return -ENOMEM; in amdgpu_display_modeset_create_props()
1384 adev->mode_info.disp_priority = 0; in amdgpu_display_update_priority()
1386 adev->mode_info.disp_priority = amdgpu_disp_priority; in amdgpu_display_update_priority()
1393 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ in amdgpu_display_is_hdtv_mode()
1394 (mode->vdisplay == 576) || /* 576p */ in amdgpu_display_is_hdtv_mode()
1395 (mode->vdisplay == 720) || /* 720p */ in amdgpu_display_is_hdtv_mode()
1396 (mode->vdisplay == 1080)) /* 1080p */ in amdgpu_display_is_hdtv_mode()
1406 struct drm_device *dev = crtc->dev; in amdgpu_display_crtc_scaling_mode_fixup()
1414 amdgpu_crtc->h_border = 0; in amdgpu_display_crtc_scaling_mode_fixup()
1415 amdgpu_crtc->v_border = 0; in amdgpu_display_crtc_scaling_mode_fixup()
1417 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in amdgpu_display_crtc_scaling_mode_fixup()
1418 if (encoder->crtc != crtc) in amdgpu_display_crtc_scaling_mode_fixup()
1424 if (amdgpu_encoder->rmx_type == RMX_OFF) in amdgpu_display_crtc_scaling_mode_fixup()
1425 amdgpu_crtc->rmx_type = RMX_OFF; in amdgpu_display_crtc_scaling_mode_fixup()
1426 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || in amdgpu_display_crtc_scaling_mode_fixup()
1427 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) in amdgpu_display_crtc_scaling_mode_fixup()
1428 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; in amdgpu_display_crtc_scaling_mode_fixup()
1430 amdgpu_crtc->rmx_type = RMX_OFF; in amdgpu_display_crtc_scaling_mode_fixup()
1432 memcpy(&amdgpu_crtc->native_mode, in amdgpu_display_crtc_scaling_mode_fixup()
1433 &amdgpu_encoder->native_mode, in amdgpu_display_crtc_scaling_mode_fixup()
1435 src_v = crtc->mode.vdisplay; in amdgpu_display_crtc_scaling_mode_fixup()
1436 dst_v = amdgpu_crtc->native_mode.vdisplay; in amdgpu_display_crtc_scaling_mode_fixup()
1437 src_h = crtc->mode.hdisplay; in amdgpu_display_crtc_scaling_mode_fixup()
1438 dst_h = amdgpu_crtc->native_mode.hdisplay; in amdgpu_display_crtc_scaling_mode_fixup()
1441 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && in amdgpu_display_crtc_scaling_mode_fixup()
1442 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || in amdgpu_display_crtc_scaling_mode_fixup()
1443 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && in amdgpu_display_crtc_scaling_mode_fixup()
1444 connector->display_info.is_hdmi && in amdgpu_display_crtc_scaling_mode_fixup()
1446 if (amdgpu_encoder->underscan_hborder != 0) in amdgpu_display_crtc_scaling_mode_fixup()
1447 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; in amdgpu_display_crtc_scaling_mode_fixup()
1449 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; in amdgpu_display_crtc_scaling_mode_fixup()
1450 if (amdgpu_encoder->underscan_vborder != 0) in amdgpu_display_crtc_scaling_mode_fixup()
1451 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; in amdgpu_display_crtc_scaling_mode_fixup()
1453 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; in amdgpu_display_crtc_scaling_mode_fixup()
1454 amdgpu_crtc->rmx_type = RMX_FULL; in amdgpu_display_crtc_scaling_mode_fixup()
1455 src_v = crtc->mode.vdisplay; in amdgpu_display_crtc_scaling_mode_fixup()
1456 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); in amdgpu_display_crtc_scaling_mode_fixup()
1457 src_h = crtc->mode.hdisplay; in amdgpu_display_crtc_scaling_mode_fixup()
1458 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); in amdgpu_display_crtc_scaling_mode_fixup()
1461 if (amdgpu_crtc->rmx_type != RMX_OFF) { in amdgpu_display_crtc_scaling_mode_fixup()
1466 amdgpu_crtc->vsc.full = dfixed_div(a, b); in amdgpu_display_crtc_scaling_mode_fixup()
1469 amdgpu_crtc->hsc.full = dfixed_div(a, b); in amdgpu_display_crtc_scaling_mode_fixup()
1471 amdgpu_crtc->vsc.full = dfixed_const(1); in amdgpu_display_crtc_scaling_mode_fixup()
1472 amdgpu_crtc->hsc.full = dfixed_const(1); in amdgpu_display_crtc_scaling_mode_fixup()
1495 * \param *stime Target location for timestamp taken immediately before
1497 * \param *etime Target location for timestamp taken immediately after
1502 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1552 vbl_start = mode->crtc_vdisplay; in amdgpu_display_get_crtc_scanoutpos()
1559 *hpos = *vpos - vbl_start; in amdgpu_display_get_crtc_scanoutpos()
1573 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; in amdgpu_display_get_crtc_scanoutpos()
1586 *vpos -= vbl_start; in amdgpu_display_get_crtc_scanoutpos()
1598 vtotal = mode->crtc_vtotal; in amdgpu_display_get_crtc_scanoutpos()
1601 * the vtotal value. Clamp to 0 to return -vbl_end instead in amdgpu_display_get_crtc_scanoutpos()
1604 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0; in amdgpu_display_get_crtc_scanoutpos()
1608 *vpos = *vpos - vbl_end; in amdgpu_display_get_crtc_scanoutpos()
1615 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) in amdgpu_display_crtc_idx_to_irq_type()
1641 struct drm_device *dev = crtc->dev; in amdgpu_crtc_get_scanout_position()
1642 unsigned int pipe = crtc->index; in amdgpu_crtc_get_scanout_position()
1652 struct drm_fb_helper *fb_helper = dev->fb_helper; in amdgpu_display_robj_is_fb()
1654 if (!fb_helper || !fb_helper->buffer) in amdgpu_display_robj_is_fb()
1657 if (gem_to_amdgpu_bo(fb_helper->buffer->gem) != robj) in amdgpu_display_robj_is_fb()
1682 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { in amdgpu_display_suspend_helper()
1684 struct drm_framebuffer *fb = crtc->primary->fb; in amdgpu_display_suspend_helper()
1687 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { in amdgpu_display_suspend_helper()
1688 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); in amdgpu_display_suspend_helper()
1697 if (!fb || !fb->obj[0]) in amdgpu_display_suspend_helper()
1700 robj = gem_to_amdgpu_bo(fb->obj[0]); in amdgpu_display_suspend_helper()
1721 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { in amdgpu_display_resume_helper()
1724 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { in amdgpu_display_resume_helper()
1725 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); in amdgpu_display_resume_helper()
1731 dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r); in amdgpu_display_resume_helper()
1732 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); in amdgpu_display_resume_helper()