Lines Matching defs:amdgpu_device
768 struct amdgpu_device { struct
769 struct device *dev;
770 struct pci_dev *pdev;
771 struct drm_device ddev;
774 struct amdgpu_acp acp;
776 struct amdgpu_hive_info *hive;
777 struct amdgpu_xcp_mgr *xcp_mgr;
779 enum amd_asic_type asic_type;
780 uint32_t family;
781 uint32_t rev_id;
782 uint32_t external_rev_id;
783 unsigned long flags;
784 unsigned long apu_flags;
785 int usec_timeout;
786 const struct amdgpu_asic_funcs *asic_funcs;
787 bool shutdown;
788 bool need_swiotlb;
789 bool accel_working;
790 struct notifier_block acpi_nb;
791 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
792 struct debugfs_blob_wrapper debugfs_vbios_blob;
793 struct debugfs_blob_wrapper debugfs_discovery_blob;
794 struct mutex srbm_mutex;
796 struct mutex grbm_idx_mutex;
797 struct dev_pm_domain vga_pm_domain;
798 bool have_disp_power_ref;
799 bool have_atomics_support;
802 bool is_atom_fw;
803 uint8_t *bios;
804 uint32_t bios_size;
805 uint32_t bios_scratch_reg_offset;
806 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
809 resource_size_t rmmio_base;
810 resource_size_t rmmio_size;
811 void __iomem *rmmio;
813 spinlock_t mmio_idx_lock;
814 struct amdgpu_mmio_remap rmmio_remap;
816 spinlock_t smc_idx_lock;
817 amdgpu_rreg_t smc_rreg;
818 amdgpu_wreg_t smc_wreg;
820 spinlock_t pcie_idx_lock;
821 amdgpu_rreg_t pcie_rreg;
822 amdgpu_wreg_t pcie_wreg;
823 amdgpu_rreg_t pciep_rreg;
824 amdgpu_wreg_t pciep_wreg;
825 amdgpu_rreg_ext_t pcie_rreg_ext;
826 amdgpu_wreg_ext_t pcie_wreg_ext;
827 amdgpu_rreg64_t pcie_rreg64;
828 amdgpu_wreg64_t pcie_wreg64;
830 spinlock_t uvd_ctx_idx_lock;
831 amdgpu_rreg_t uvd_ctx_rreg;
832 amdgpu_wreg_t uvd_ctx_wreg;
834 spinlock_t didt_idx_lock;
835 amdgpu_rreg_t didt_rreg;
836 amdgpu_wreg_t didt_wreg;
838 spinlock_t gc_cac_idx_lock;
839 amdgpu_rreg_t gc_cac_rreg;
840 amdgpu_wreg_t gc_cac_wreg;
842 spinlock_t se_cac_idx_lock;
843 amdgpu_rreg_t se_cac_rreg;
844 amdgpu_wreg_t se_cac_wreg;
846 spinlock_t audio_endpt_idx_lock;
847 amdgpu_block_rreg_t audio_endpt_rreg;
848 amdgpu_block_wreg_t audio_endpt_wreg;
849 struct amdgpu_doorbell doorbell;
852 struct amdgpu_clock clock;
855 struct amdgpu_gmc gmc;
856 struct amdgpu_gart gart;
857 dma_addr_t dummy_page_addr;
858 struct amdgpu_vm_manager vm_manager;
859 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
885 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ argument
886 struct delayed_work hotplug_work;
887 struct amdgpu_irq_src crtc_irq;
888 struct amdgpu_irq_src vline0_irq;
889 struct amdgpu_irq_src vupdate_irq;
890 struct amdgpu_irq_src pageflip_irq;
891 struct amdgpu_irq_src hpd_irq;
892 struct amdgpu_irq_src dmub_trace_irq;
893 struct amdgpu_irq_src dmub_outbox_irq;
896 u64 fence_context;
897 unsigned num_rings;
898 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
899 struct dma_fence __rcu *gang_submit;
900 bool ib_pool_ready;
901 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
902 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
905 struct amdgpu_irq irq;
908 struct amd_powerplay powerplay;
909 struct amdgpu_pm pm;
910 u64 cg_flags;
911 u32 pg_flags;
914 struct amdgpu_nbio nbio;
917 struct amdgpu_hdp hdp;
920 struct amdgpu_smuio smuio;
923 struct amdgpu_mmhub mmhub;
926 struct amdgpu_gfxhub gfxhub;
929 struct amdgpu_gfx gfx;
932 struct amdgpu_sdma sdma;
935 struct amdgpu_lsdma lsdma;
938 struct amdgpu_uvd uvd;
941 struct amdgpu_vce vce;
944 struct amdgpu_vcn vcn;
947 struct amdgpu_jpeg jpeg;
950 struct amdgpu_firmware firmware;
953 struct psp_context psp;
956 struct amdgpu_gds gds;
959 struct amdgpu_kfd_dev kfd;
962 struct amdgpu_umc umc;
965 struct amdgpu_display_manager dm;
968 bool enable_mes;
969 bool enable_mes_kiq;
970 struct amdgpu_mes mes;
971 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM];
974 struct amdgpu_df df;
977 struct amdgpu_mca mca;
979 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
980 uint32_t harvest_ip_mask;
981 int num_ip_blocks;
982 struct mutex mn_lock;
986 atomic64_t vram_pin_size;
987 atomic64_t visible_pin_size;
988 atomic64_t gart_pin_size;
991 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
992 struct amdgpu_ip_map_info ip_map;
995 struct delayed_work delayed_init_work;
997 struct amdgpu_virt virt;
1000 struct list_head shadow_list;
1001 struct mutex shadow_list_lock;
1004 bool has_hw_reset;
1005 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
1008 bool in_suspend;
1009 bool in_s3;
1010 bool in_s4;
1011 bool in_s0ix;
1013 bool suspend_complete;
1015 enum pp_mp1_state mp1_state;
1016 struct amdgpu_doorbell_index doorbell_index;
1018 struct mutex notifier_lock;
1020 int asic_reset_res;
1021 struct work_struct xgmi_reset_work;
1022 struct list_head reset_list;
1024 long gfx_timeout;
1025 long sdma_timeout;
1026 long video_timeout;
1027 long compute_timeout;
1029 uint64_t unique_id;
1030 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1033 bool in_runpm;
1034 bool has_pr3;
1036 bool ucode_sysfs_en;
1039 char product_number[20];
1040 char product_name[AMDGPU_PRODUCT_NAME_LEN];
1041 char serial[20];
1043 atomic_t throttling_logging_enabled;
1044 struct ratelimit_state throttling_logging_rs;
1045 uint32_t ras_hw_enabled;
1046 uint32_t ras_enabled;
1048 bool no_hw_access;
1049 struct pci_saved_state *pci_state;
1050 pci_channel_state_t pci_channel_state;
1053 bool barrier_has_auto_waitcnt;
1055 struct amdgpu_reset_control *reset_cntl;
1056 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
1058 bool ram_is_direct_mapped;
1060 struct list_head ras_list;
1062 struct ip_discovery_top *ip_top;
1064 struct amdgpu_reset_domain *reset_domain;
1089 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) in drm_to_adev() argument