Lines Matching +full:port +full:- +full:base
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2022 NVIDIA Corporation
18 #include <dt-bindings/gpio/tegra186-gpio.h>
19 #include <dt-bindings/gpio/tegra194-gpio.h>
20 #include <dt-bindings/gpio/tegra234-gpio.h>
21 #include <dt-bindings/gpio/tegra241-gpio.h>
73 unsigned int port; member
107 void __iomem *base; member
115 for (i = 0; i < gpio->soc->num_ports; i++) { in tegra186_gpio_get_port()
116 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; in tegra186_gpio_get_port() local
118 if (*pin >= start && *pin < start + port->pins) { in tegra186_gpio_get_port()
119 *pin -= start; in tegra186_gpio_get_port()
120 return port; in tegra186_gpio_get_port()
123 start += port->pins; in tegra186_gpio_get_port()
132 const struct tegra_gpio_port *port; in tegra186_gpio_get_base() local
135 port = tegra186_gpio_get_port(gpio, &pin); in tegra186_gpio_get_base()
136 if (!port) in tegra186_gpio_get_base()
139 offset = port->bank * 0x1000 + port->port * 0x200; in tegra186_gpio_get_base()
141 return gpio->base + offset + pin * 0x20; in tegra186_gpio_get_base()
147 const struct tegra_gpio_port *port; in tegra186_gpio_get_secure_base() local
150 port = tegra186_gpio_get_port(gpio, &pin); in tegra186_gpio_get_secure_base()
151 if (!port) in tegra186_gpio_get_secure_base()
154 offset = port->bank * 0x1000 + port->port * TEGRA186_GPIO_SCR_PORT_SIZE; in tegra186_gpio_get_secure_base()
156 return gpio->secure + offset + pin * TEGRA186_GPIO_SCR_PIN_SIZE; in tegra186_gpio_get_secure_base()
166 if (gpio->soc->has_vm_support) { in tegra186_gpio_is_accessible()
208 void __iomem *base; in tegra186_gpio_get_direction() local
211 base = tegra186_gpio_get_base(gpio, offset); in tegra186_gpio_get_direction()
212 if (WARN_ON(base == NULL)) in tegra186_gpio_get_direction()
213 return -ENODEV; in tegra186_gpio_get_direction()
215 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_get_direction()
226 void __iomem *base; in tegra186_gpio_direction_input() local
229 base = tegra186_gpio_get_base(gpio, offset); in tegra186_gpio_direction_input()
230 if (WARN_ON(base == NULL)) in tegra186_gpio_direction_input()
231 return -ENODEV; in tegra186_gpio_direction_input()
233 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); in tegra186_gpio_direction_input()
235 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); in tegra186_gpio_direction_input()
237 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_direction_input()
240 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_direction_input()
249 void __iomem *base; in tegra186_gpio_direction_output() local
253 chip->set(chip, offset, level); in tegra186_gpio_direction_output()
255 base = tegra186_gpio_get_base(gpio, offset); in tegra186_gpio_direction_output()
256 if (WARN_ON(base == NULL)) in tegra186_gpio_direction_output()
257 return -EINVAL; in tegra186_gpio_direction_output()
260 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); in tegra186_gpio_direction_output()
262 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); in tegra186_gpio_direction_output()
264 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_direction_output()
267 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_direction_output()
278 void __iomem *base; in tegra186_gpio_en_hw_ts() local
282 return -EINVAL; in tegra186_gpio_en_hw_ts()
286 return -ENODEV; in tegra186_gpio_en_hw_ts()
288 base = tegra186_gpio_get_base(gpio, offset); in tegra186_gpio_en_hw_ts()
289 if (WARN_ON(base == NULL)) in tegra186_gpio_en_hw_ts()
290 return -EINVAL; in tegra186_gpio_en_hw_ts()
292 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_en_hw_ts()
304 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_en_hw_ts()
313 void __iomem *base; in tegra186_gpio_dis_hw_ts() local
317 return -EINVAL; in tegra186_gpio_dis_hw_ts()
321 return -ENODEV; in tegra186_gpio_dis_hw_ts()
323 base = tegra186_gpio_get_base(gpio, offset); in tegra186_gpio_dis_hw_ts()
324 if (WARN_ON(base == NULL)) in tegra186_gpio_dis_hw_ts()
325 return -EINVAL; in tegra186_gpio_dis_hw_ts()
327 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_dis_hw_ts()
337 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_dis_hw_ts()
345 void __iomem *base; in tegra186_gpio_get() local
348 base = tegra186_gpio_get_base(gpio, offset); in tegra186_gpio_get()
349 if (WARN_ON(base == NULL)) in tegra186_gpio_get()
350 return -ENODEV; in tegra186_gpio_get()
352 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_get()
354 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); in tegra186_gpio_get()
356 value = readl(base + TEGRA186_GPIO_INPUT); in tegra186_gpio_get()
365 void __iomem *base; in tegra186_gpio_set() local
368 base = tegra186_gpio_get_base(gpio, offset); in tegra186_gpio_set()
369 if (WARN_ON(base == NULL)) in tegra186_gpio_set()
372 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); in tegra186_gpio_set()
378 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE); in tegra186_gpio_set()
387 void __iomem *base; in tegra186_gpio_set_config() local
389 base = tegra186_gpio_get_base(gpio, offset); in tegra186_gpio_set_config()
390 if (base == NULL) in tegra186_gpio_set_config()
391 return -ENXIO; in tegra186_gpio_set_config()
394 return -ENOTSUPP; in tegra186_gpio_set_config()
403 return -EINVAL; in tegra186_gpio_set_config()
408 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL); in tegra186_gpio_set_config()
410 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_set_config()
412 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_set_config()
425 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0) in tegra186_gpio_add_pin_ranges()
428 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux); in tegra186_gpio_add_pin_ranges()
430 return -ENODEV; in tegra186_gpio_add_pin_ranges()
435 return -EPROBE_DEFER; in tegra186_gpio_add_pin_ranges()
437 for (i = 0; i < gpio->soc->num_pin_ranges; i++) { in tegra186_gpio_add_pin_ranges()
438 unsigned int pin = gpio->soc->pin_ranges[i].offset, port; in tegra186_gpio_add_pin_ranges() local
439 const char *group = gpio->soc->pin_ranges[i].group; in tegra186_gpio_add_pin_ranges()
441 port = pin / 8; in tegra186_gpio_add_pin_ranges()
444 if (port >= gpio->soc->num_ports) { in tegra186_gpio_add_pin_ranges()
445 dev_warn(chip->parent, "invalid port %u for %s\n", in tegra186_gpio_add_pin_ranges()
446 port, group); in tegra186_gpio_add_pin_ranges()
450 for (j = 0; j < port; j++) in tegra186_gpio_add_pin_ranges()
451 pin += gpio->soc->ports[j].pins; in tegra186_gpio_add_pin_ranges()
466 unsigned int port, pin, i, offset = 0; in tegra186_gpio_of_xlate() local
468 if (WARN_ON(chip->of_gpio_n_cells < 2)) in tegra186_gpio_of_xlate()
469 return -EINVAL; in tegra186_gpio_of_xlate()
471 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells)) in tegra186_gpio_of_xlate()
472 return -EINVAL; in tegra186_gpio_of_xlate()
474 port = spec->args[0] / 8; in tegra186_gpio_of_xlate()
475 pin = spec->args[0] % 8; in tegra186_gpio_of_xlate()
477 if (port >= gpio->soc->num_ports) { in tegra186_gpio_of_xlate()
478 dev_err(chip->parent, "invalid port number: %u\n", port); in tegra186_gpio_of_xlate()
479 return -EINVAL; in tegra186_gpio_of_xlate()
482 for (i = 0; i < port; i++) in tegra186_gpio_of_xlate()
483 offset += gpio->soc->ports[i].pins; in tegra186_gpio_of_xlate()
486 *flags = spec->args[1]; in tegra186_gpio_of_xlate()
497 void __iomem *base; in tegra186_irq_ack() local
499 base = tegra186_gpio_get_base(gpio, data->hwirq); in tegra186_irq_ack()
500 if (WARN_ON(base == NULL)) in tegra186_irq_ack()
503 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR); in tegra186_irq_ack()
510 void __iomem *base; in tegra186_irq_mask() local
513 base = tegra186_gpio_get_base(gpio, data->hwirq); in tegra186_irq_mask()
514 if (WARN_ON(base == NULL)) in tegra186_irq_mask()
517 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_irq_mask()
519 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_irq_mask()
521 gpiochip_disable_irq(&gpio->gpio, data->hwirq); in tegra186_irq_mask()
528 void __iomem *base; in tegra186_irq_unmask() local
531 base = tegra186_gpio_get_base(gpio, data->hwirq); in tegra186_irq_unmask()
532 if (WARN_ON(base == NULL)) in tegra186_irq_unmask()
535 gpiochip_enable_irq(&gpio->gpio, data->hwirq); in tegra186_irq_unmask()
537 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_irq_unmask()
539 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_irq_unmask()
546 void __iomem *base; in tegra186_irq_set_type() local
549 base = tegra186_gpio_get_base(gpio, data->hwirq); in tegra186_irq_set_type()
550 if (WARN_ON(base == NULL)) in tegra186_irq_set_type()
551 return -ENODEV; in tegra186_irq_set_type()
553 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_irq_set_type()
584 return -EINVAL; in tegra186_irq_set_type()
587 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_irq_set_type()
594 if (data->parent_data) in tegra186_irq_set_type()
602 if (data->parent_data) in tegra186_irq_set_wake()
612 seq_printf(p, dev_name(gc->parent)); in tegra186_irq_print_chip()
629 struct irq_domain *domain = gpio->gpio.irq.domain; in tegra186_gpio_irq()
636 for (i = 0; i < gpio->soc->num_ports; i++) { in tegra186_gpio_irq()
637 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; in tegra186_gpio_irq() local
640 void __iomem *base; in tegra186_gpio_irq() local
642 base = gpio->base + port->bank * 0x1000 + port->port * 0x200; in tegra186_gpio_irq()
645 for (j = 0; j < gpio->num_irqs_per_bank; j++) { in tegra186_gpio_irq()
646 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j]) in tegra186_gpio_irq()
650 if (j == gpio->num_irqs_per_bank) in tegra186_gpio_irq()
653 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); in tegra186_gpio_irq()
655 for_each_set_bit(pin, &value, port->pins) { in tegra186_gpio_irq()
661 offset += port->pins; in tegra186_gpio_irq()
672 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data); in tegra186_gpio_irq_domain_translate()
673 unsigned int port, pin, i, offset = 0; in tegra186_gpio_irq_domain_translate() local
675 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2)) in tegra186_gpio_irq_domain_translate()
676 return -EINVAL; in tegra186_gpio_irq_domain_translate()
678 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells)) in tegra186_gpio_irq_domain_translate()
679 return -EINVAL; in tegra186_gpio_irq_domain_translate()
681 port = fwspec->param[0] / 8; in tegra186_gpio_irq_domain_translate()
682 pin = fwspec->param[0] % 8; in tegra186_gpio_irq_domain_translate()
684 if (port >= gpio->soc->num_ports) in tegra186_gpio_irq_domain_translate()
685 return -EINVAL; in tegra186_gpio_irq_domain_translate()
687 for (i = 0; i < port; i++) in tegra186_gpio_irq_domain_translate()
688 offset += gpio->soc->ports[i].pins; in tegra186_gpio_irq_domain_translate()
690 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; in tegra186_gpio_irq_domain_translate()
702 struct irq_fwspec *fwspec = &gfwspec->fwspec; in tegra186_gpio_populate_parent_fwspec()
704 fwspec->fwnode = chip->irq.parent_domain->fwnode; in tegra186_gpio_populate_parent_fwspec()
705 fwspec->param_count = 3; in tegra186_gpio_populate_parent_fwspec()
706 fwspec->param[0] = gpio->soc->instance; in tegra186_gpio_populate_parent_fwspec()
707 fwspec->param[1] = parent_hwirq; in tegra186_gpio_populate_parent_fwspec()
708 fwspec->param[2] = parent_type; in tegra186_gpio_populate_parent_fwspec()
719 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq); in tegra186_gpio_child_to_parent_hwirq()
731 for (i = 0; i < gpio->soc->num_ports; i++) { in tegra186_gpio_child_offset_to_irq()
732 if (offset < gpio->soc->ports[i].pins) in tegra186_gpio_child_offset_to_irq()
735 offset -= gpio->soc->ports[i].pins; in tegra186_gpio_child_offset_to_irq()
742 { .compatible = "nvidia,tegra186-pmc" },
743 { .compatible = "nvidia,tegra194-pmc" },
744 { .compatible = "nvidia,tegra234-pmc" },
750 struct device *dev = gpio->gpio.parent; in tegra186_gpio_init_route_mapping()
754 for (i = 0; i < gpio->soc->num_ports; i++) { in tegra186_gpio_init_route_mapping()
755 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; in tegra186_gpio_init_route_mapping() local
756 unsigned int offset, p = port->port; in tegra186_gpio_init_route_mapping()
757 void __iomem *base; in tegra186_gpio_init_route_mapping() local
759 base = gpio->secure + port->bank * 0x1000 + 0x800; in tegra186_gpio_init_route_mapping()
761 value = readl(base + TEGRA186_GPIO_CTL_SCR); in tegra186_gpio_init_route_mapping()
773 dev_dbg(dev, "programming default interrupt routing for port %s\n", in tegra186_gpio_init_route_mapping()
774 port->name); in tegra186_gpio_init_route_mapping()
787 value = readl(base + offset); in tegra186_gpio_init_route_mapping()
788 value = BIT(port->pins) - 1; in tegra186_gpio_init_route_mapping()
789 writel(value, base + offset); in tegra186_gpio_init_route_mapping()
796 struct device *dev = gpio->gpio.parent; in tegra186_gpio_irqs_per_bank()
798 if (gpio->num_irq > gpio->num_banks) { in tegra186_gpio_irqs_per_bank()
799 if (gpio->num_irq % gpio->num_banks != 0) in tegra186_gpio_irqs_per_bank()
803 if (gpio->num_irq < gpio->num_banks) in tegra186_gpio_irqs_per_bank()
806 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks; in tegra186_gpio_irqs_per_bank()
808 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank) in tegra186_gpio_irqs_per_bank()
815 gpio->num_irq, gpio->num_banks); in tegra186_gpio_irqs_per_bank()
816 return -EINVAL; in tegra186_gpio_irqs_per_bank()
828 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); in tegra186_gpio_probe()
830 return -ENOMEM; in tegra186_gpio_probe()
832 gpio->soc = device_get_match_data(&pdev->dev); in tegra186_gpio_probe()
833 gpio->gpio.label = gpio->soc->name; in tegra186_gpio_probe()
834 gpio->gpio.parent = &pdev->dev; in tegra186_gpio_probe()
837 for (i = 0; i < gpio->soc->num_ports; i++) in tegra186_gpio_probe()
838 if (gpio->soc->ports[i].bank > gpio->num_banks) in tegra186_gpio_probe()
839 gpio->num_banks = gpio->soc->ports[i].bank; in tegra186_gpio_probe()
841 gpio->num_banks++; in tegra186_gpio_probe()
844 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security"); in tegra186_gpio_probe()
845 if (IS_ERR(gpio->secure)) { in tegra186_gpio_probe()
846 gpio->secure = devm_platform_ioremap_resource(pdev, 0); in tegra186_gpio_probe()
847 if (IS_ERR(gpio->secure)) in tegra186_gpio_probe()
848 return PTR_ERR(gpio->secure); in tegra186_gpio_probe()
851 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio"); in tegra186_gpio_probe()
852 if (IS_ERR(gpio->base)) { in tegra186_gpio_probe()
853 gpio->base = devm_platform_ioremap_resource(pdev, 1); in tegra186_gpio_probe()
854 if (IS_ERR(gpio->base)) in tegra186_gpio_probe()
855 return PTR_ERR(gpio->base); in tegra186_gpio_probe()
862 gpio->num_irq = err; in tegra186_gpio_probe()
868 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq), in tegra186_gpio_probe()
870 if (!gpio->irq) in tegra186_gpio_probe()
871 return -ENOMEM; in tegra186_gpio_probe()
873 for (i = 0; i < gpio->num_irq; i++) { in tegra186_gpio_probe()
878 gpio->irq[i] = err; in tegra186_gpio_probe()
881 gpio->gpio.request = gpiochip_generic_request; in tegra186_gpio_probe()
882 gpio->gpio.free = gpiochip_generic_free; in tegra186_gpio_probe()
883 gpio->gpio.get_direction = tegra186_gpio_get_direction; in tegra186_gpio_probe()
884 gpio->gpio.direction_input = tegra186_gpio_direction_input; in tegra186_gpio_probe()
885 gpio->gpio.direction_output = tegra186_gpio_direction_output; in tegra186_gpio_probe()
886 gpio->gpio.get = tegra186_gpio_get; in tegra186_gpio_probe()
887 gpio->gpio.set = tegra186_gpio_set; in tegra186_gpio_probe()
888 gpio->gpio.set_config = tegra186_gpio_set_config; in tegra186_gpio_probe()
889 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges; in tegra186_gpio_probe()
890 gpio->gpio.init_valid_mask = tegra186_init_valid_mask; in tegra186_gpio_probe()
891 if (gpio->soc->has_gte) { in tegra186_gpio_probe()
892 gpio->gpio.en_hw_timestamp = tegra186_gpio_en_hw_ts; in tegra186_gpio_probe()
893 gpio->gpio.dis_hw_timestamp = tegra186_gpio_dis_hw_ts; in tegra186_gpio_probe()
896 gpio->gpio.base = -1; in tegra186_gpio_probe()
898 for (i = 0; i < gpio->soc->num_ports; i++) in tegra186_gpio_probe()
899 gpio->gpio.ngpio += gpio->soc->ports[i].pins; in tegra186_gpio_probe()
901 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio, in tegra186_gpio_probe()
904 return -ENOMEM; in tegra186_gpio_probe()
906 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { in tegra186_gpio_probe()
907 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; in tegra186_gpio_probe() local
910 for (j = 0; j < port->pins; j++) { in tegra186_gpio_probe()
911 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL, in tegra186_gpio_probe()
912 "P%s.%02x", port->name, j); in tegra186_gpio_probe()
914 return -ENOMEM; in tegra186_gpio_probe()
919 offset += port->pins; in tegra186_gpio_probe()
922 gpio->gpio.names = (const char * const *)names; in tegra186_gpio_probe()
925 gpio->gpio.of_gpio_n_cells = 2; in tegra186_gpio_probe()
926 gpio->gpio.of_xlate = tegra186_gpio_of_xlate; in tegra186_gpio_probe()
929 irq = &gpio->gpio.irq; in tegra186_gpio_probe()
931 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node); in tegra186_gpio_probe()
932 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq; in tegra186_gpio_probe()
933 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec; in tegra186_gpio_probe()
934 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq; in tegra186_gpio_probe()
935 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate; in tegra186_gpio_probe()
936 irq->handler = handle_simple_irq; in tegra186_gpio_probe()
937 irq->default_type = IRQ_TYPE_NONE; in tegra186_gpio_probe()
938 irq->parent_handler = tegra186_gpio_irq; in tegra186_gpio_probe()
939 irq->parent_handler_data = gpio; in tegra186_gpio_probe()
940 irq->num_parents = gpio->num_irq; in tegra186_gpio_probe()
949 if (gpio->num_irqs_per_bank > 1) { in tegra186_gpio_probe()
950 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks, in tegra186_gpio_probe()
951 sizeof(*irq->parents), GFP_KERNEL); in tegra186_gpio_probe()
952 if (!irq->parents) in tegra186_gpio_probe()
953 return -ENOMEM; in tegra186_gpio_probe()
955 for (i = 0; i < gpio->num_banks; i++) in tegra186_gpio_probe()
956 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank]; in tegra186_gpio_probe()
958 irq->num_parents = gpio->num_banks; in tegra186_gpio_probe()
960 irq->num_parents = gpio->num_irq; in tegra186_gpio_probe()
961 irq->parents = gpio->irq; in tegra186_gpio_probe()
964 if (gpio->soc->num_irqs_per_bank > 1) in tegra186_gpio_probe()
970 irq->parent_domain = irq_find_host(np); in tegra186_gpio_probe()
973 if (!irq->parent_domain) in tegra186_gpio_probe()
974 return -EPROBE_DEFER; in tegra186_gpio_probe()
980 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio, in tegra186_gpio_probe()
981 sizeof(*irq->map), GFP_KERNEL); in tegra186_gpio_probe()
982 if (!irq->map) in tegra186_gpio_probe()
983 return -ENOMEM; in tegra186_gpio_probe()
985 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { in tegra186_gpio_probe()
986 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; in tegra186_gpio_probe() local
988 for (j = 0; j < port->pins; j++) in tegra186_gpio_probe()
989 irq->map[offset + j] = irq->parents[port->bank]; in tegra186_gpio_probe()
991 offset += port->pins; in tegra186_gpio_probe()
994 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio); in tegra186_gpio_probe()
1001 .port = _port, \
1034 .name = "tegra186-gpio",
1044 .port = _port, \
1062 .name = "tegra186-gpio-aon",
1072 .port = _port, \
1115 .name = "tegra194-gpio",
1120 .pinmux = "nvidia,tegra194-pinmux",
1128 .port = _port, \
1143 .name = "tegra194-gpio-aon",
1154 .port = _port, \
1189 .name = "tegra234-gpio",
1199 .port = _port, \
1215 .name = "tegra234-gpio-aon",
1226 .port = _port, \
1247 .name = "tegra241-gpio",
1257 .port = _port, \
1269 .name = "tegra241-gpio-aon",
1277 .compatible = "nvidia,tegra186-gpio",
1280 .compatible = "nvidia,tegra186-gpio-aon",
1283 .compatible = "nvidia,tegra194-gpio",
1286 .compatible = "nvidia,tegra194-gpio-aon",
1289 .compatible = "nvidia,tegra234-gpio",
1292 .compatible = "nvidia,tegra234-gpio-aon",
1313 .name = "tegra186-gpio",