42 static void sifive_gpio_set_ie(struct sifive_gpio *chip, unsigned int offset)  in sifive_gpio_set_ie()  argument
47 	raw_spin_lock_irqsave(&chip->gc.bgpio_lock, flags);  in sifive_gpio_set_ie()
48 	trigger = (chip->irq_state & BIT(offset)) ? chip->trigger[offset] : 0;  in sifive_gpio_set_ie()
49 	regmap_update_bits(chip->regs, SIFIVE_GPIO_RISE_IE, BIT(offset),  in sifive_gpio_set_ie()
51 	regmap_update_bits(chip->regs, SIFIVE_GPIO_FALL_IE, BIT(offset),  in sifive_gpio_set_ie()
53 	regmap_update_bits(chip->regs, SIFIVE_GPIO_HIGH_IE, BIT(offset),  in sifive_gpio_set_ie()
55 	regmap_update_bits(chip->regs, SIFIVE_GPIO_LOW_IE, BIT(offset),  in sifive_gpio_set_ie()
57 	raw_spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags);  in sifive_gpio_set_ie()
63 	struct sifive_gpio *chip = gpiochip_get_data(gc);  in sifive_gpio_irq_set_type()  local
69 	chip->trigger[offset] = trigger;  in sifive_gpio_irq_set_type()
70 	sifive_gpio_set_ie(chip, offset);  in sifive_gpio_irq_set_type()
77 	struct sifive_gpio *chip = gpiochip_get_data(gc);  in sifive_gpio_irq_enable()  local
91 	regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);  in sifive_gpio_irq_enable()
92 	regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);  in sifive_gpio_irq_enable()
93 	regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);  in sifive_gpio_irq_enable()
94 	regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);  in sifive_gpio_irq_enable()
98 	assign_bit(offset, &chip->irq_state, 1);  in sifive_gpio_irq_enable()
99 	sifive_gpio_set_ie(chip, offset);  in sifive_gpio_irq_enable()
105 	struct sifive_gpio *chip = gpiochip_get_data(gc);  in sifive_gpio_irq_disable()  local
109 	assign_bit(offset, &chip->irq_state, 0);  in sifive_gpio_irq_disable()
110 	sifive_gpio_set_ie(chip, offset);  in sifive_gpio_irq_disable()
118 	struct sifive_gpio *chip = gpiochip_get_data(gc);  in sifive_gpio_irq_eoi()  local
125 	regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);  in sifive_gpio_irq_eoi()
126 	regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);  in sifive_gpio_irq_eoi()
127 	regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);  in sifive_gpio_irq_eoi()
128 	regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);  in sifive_gpio_irq_eoi()
164 	struct sifive_gpio *chip = gpiochip_get_data(gc);  in sifive_gpio_child_to_parent_hwirq()  local
165 	struct irq_data *d = irq_get_irq_data(chip->irq_number[child]);  in sifive_gpio_child_to_parent_hwirq()
186 	struct sifive_gpio *chip;  in sifive_gpio_probe()  local
189 	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);  in sifive_gpio_probe()
190 	if (!chip)  in sifive_gpio_probe()
193 	chip->base = devm_platform_ioremap_resource(pdev, 0);  in sifive_gpio_probe()
194 	if (IS_ERR(chip->base)) {  in sifive_gpio_probe()
196 		return PTR_ERR(chip->base);  in sifive_gpio_probe()
199 	chip->regs = devm_regmap_init_mmio(dev, chip->base,  in sifive_gpio_probe()
201 	if (IS_ERR(chip->regs))  in sifive_gpio_probe()
202 		return PTR_ERR(chip->regs);  in sifive_gpio_probe()
208 		chip->irq_number[ngpio] = ret;  in sifive_gpio_probe()
219 	parent = irq_get_irq_data(chip->irq_number[0])->domain;  in sifive_gpio_probe()
221 	ret = bgpio_init(&chip->gc, dev, 4,  in sifive_gpio_probe()
222 			 chip->base + SIFIVE_GPIO_INPUT_VAL,  in sifive_gpio_probe()
223 			 chip->base + SIFIVE_GPIO_OUTPUT_VAL,  in sifive_gpio_probe()
225 			 chip->base + SIFIVE_GPIO_OUTPUT_EN,  in sifive_gpio_probe()
226 			 chip->base + SIFIVE_GPIO_INPUT_EN,  in sifive_gpio_probe()
234 	regmap_write(chip->regs, SIFIVE_GPIO_RISE_IE, 0);  in sifive_gpio_probe()
235 	regmap_write(chip->regs, SIFIVE_GPIO_FALL_IE, 0);  in sifive_gpio_probe()
236 	regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IE, 0);  in sifive_gpio_probe()
237 	regmap_write(chip->regs, SIFIVE_GPIO_LOW_IE, 0);  in sifive_gpio_probe()
238 	chip->irq_state = 0;  in sifive_gpio_probe()
240 	chip->gc.base = -1;  in sifive_gpio_probe()
241 	chip->gc.ngpio = ngpio;  in sifive_gpio_probe()
242 	chip->gc.label = dev_name(dev);  in sifive_gpio_probe()
243 	chip->gc.parent = dev;  in sifive_gpio_probe()
244 	chip->gc.owner = THIS_MODULE;  in sifive_gpio_probe()
245 	girq = &chip->gc.irq;  in sifive_gpio_probe()
253 	platform_set_drvdata(pdev, chip);  in sifive_gpio_probe()
254 	return gpiochip_add_data(&chip->gc, chip);  in sifive_gpio_probe()