Lines Matching refs:mvchip
103 struct mvebu_gpio_chip *mvchip; member
138 static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip, in mvebu_gpioreg_edge_cause() argument
143 switch (mvchip->soc_variant) { in mvebu_gpioreg_edge_cause()
147 *map = mvchip->regs; in mvebu_gpioreg_edge_cause()
148 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset; in mvebu_gpioreg_edge_cause()
152 *map = mvchip->percpu_regs; in mvebu_gpioreg_edge_cause()
161 mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip) in mvebu_gpio_read_edge_cause() argument
167 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); in mvebu_gpio_read_edge_cause()
174 mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val) in mvebu_gpio_write_edge_cause() argument
179 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); in mvebu_gpio_write_edge_cause()
184 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip, in mvebu_gpioreg_edge_mask() argument
189 switch (mvchip->soc_variant) { in mvebu_gpioreg_edge_mask()
192 *map = mvchip->regs; in mvebu_gpioreg_edge_mask()
193 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset; in mvebu_gpioreg_edge_mask()
197 *map = mvchip->regs; in mvebu_gpioreg_edge_mask()
202 *map = mvchip->percpu_regs; in mvebu_gpioreg_edge_mask()
211 mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip) in mvebu_gpio_read_edge_mask() argument
217 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); in mvebu_gpio_read_edge_mask()
224 mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val) in mvebu_gpio_write_edge_mask() argument
229 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); in mvebu_gpio_write_edge_mask()
234 mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip, in mvebu_gpioreg_level_mask() argument
239 switch (mvchip->soc_variant) { in mvebu_gpioreg_level_mask()
242 *map = mvchip->regs; in mvebu_gpioreg_level_mask()
243 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset; in mvebu_gpioreg_level_mask()
247 *map = mvchip->regs; in mvebu_gpioreg_level_mask()
252 *map = mvchip->percpu_regs; in mvebu_gpioreg_level_mask()
261 mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip) in mvebu_gpio_read_level_mask() argument
267 mvebu_gpioreg_level_mask(mvchip, &map, &offset); in mvebu_gpio_read_level_mask()
274 mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val) in mvebu_gpio_write_level_mask() argument
279 mvebu_gpioreg_level_mask(mvchip, &map, &offset); in mvebu_gpio_write_level_mask()
302 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); in mvebu_gpio_set() local
304 regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, in mvebu_gpio_set()
310 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); in mvebu_gpio_get() local
313 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); in mvebu_gpio_get()
318 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, in mvebu_gpio_get()
320 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_get()
324 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u); in mvebu_gpio_get()
333 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); in mvebu_gpio_blink() local
335 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, in mvebu_gpio_blink()
341 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); in mvebu_gpio_direction_input() local
352 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_direction_input()
361 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); in mvebu_gpio_direction_output() local
375 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_direction_output()
383 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); in mvebu_gpio_get_direction() local
386 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); in mvebu_gpio_get_direction()
396 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); in mvebu_gpio_to_irq() local
398 return irq_create_mapping(mvchip->domain, pin); in mvebu_gpio_to_irq()
407 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_irq_ack() local
411 mvebu_gpio_write_edge_cause(mvchip, ~mask); in mvebu_gpio_irq_ack()
418 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_edge_irq_mask() local
424 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_edge_irq_mask()
431 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_edge_irq_unmask() local
436 mvebu_gpio_write_edge_cause(mvchip, ~mask); in mvebu_gpio_edge_irq_unmask()
438 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_edge_irq_unmask()
445 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_level_irq_mask() local
451 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_level_irq_mask()
458 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_level_irq_unmask() local
464 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_level_irq_unmask()
498 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_irq_set_type() local
504 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); in mvebu_gpio_irq_set_type()
523 regmap_update_bits(mvchip->regs, in mvebu_gpio_irq_set_type()
524 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_set_type()
529 regmap_update_bits(mvchip->regs, in mvebu_gpio_irq_set_type()
530 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_set_type()
536 regmap_read(mvchip->regs, in mvebu_gpio_irq_set_type()
537 GPIO_IN_POL_OFF + mvchip->offset, &in_pol); in mvebu_gpio_irq_set_type()
538 regmap_read(mvchip->regs, in mvebu_gpio_irq_set_type()
539 GPIO_DATA_IN_OFF + mvchip->offset, &data_in); in mvebu_gpio_irq_set_type()
549 regmap_update_bits(mvchip->regs, in mvebu_gpio_irq_set_type()
550 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_set_type()
560 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc); in mvebu_gpio_irq_handler() local
565 if (mvchip == NULL) in mvebu_gpio_irq_handler()
570 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); in mvebu_gpio_irq_handler()
571 level_mask = mvebu_gpio_read_level_mask(mvchip); in mvebu_gpio_irq_handler()
572 edge_cause = mvebu_gpio_read_edge_cause(mvchip); in mvebu_gpio_irq_handler()
573 edge_mask = mvebu_gpio_read_edge_mask(mvchip); in mvebu_gpio_irq_handler()
577 for (i = 0; i < mvchip->chip.ngpio; i++) { in mvebu_gpio_irq_handler()
580 irq = irq_find_mapping(mvchip->domain, i); in mvebu_gpio_irq_handler()
590 regmap_read(mvchip->regs, in mvebu_gpio_irq_handler()
591 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_handler()
594 regmap_write(mvchip->regs, in mvebu_gpio_irq_handler()
595 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_handler()
623 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; in mvebu_pwm_request() local
633 desc = gpiochip_request_own_desc(&mvchip->chip, in mvebu_pwm_request()
666 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; in mvebu_pwm_get_state() local
690 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u); in mvebu_pwm_get_state()
705 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; in mvebu_pwm_apply() local
745 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1); in mvebu_pwm_apply()
747 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0); in mvebu_pwm_apply()
762 static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip) in mvebu_pwm_suspend() argument
764 struct mvebu_pwm *mvpwm = mvchip->mvpwm; in mvebu_pwm_suspend()
766 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, in mvebu_pwm_suspend()
774 static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip) in mvebu_pwm_resume() argument
776 struct mvebu_pwm *mvpwm = mvchip->mvpwm; in mvebu_pwm_resume()
778 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, in mvebu_pwm_resume()
787 struct mvebu_gpio_chip *mvchip, in mvebu_pwm_probe() argument
796 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { in mvebu_pwm_probe()
813 if (IS_ERR(mvchip->clk)) in mvebu_pwm_probe()
814 return PTR_ERR(mvchip->clk); in mvebu_pwm_probe()
819 mvchip->mvpwm = mvpwm; in mvebu_pwm_probe()
820 mvpwm->mvchip = mvchip; in mvebu_pwm_probe()
823 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { in mvebu_pwm_probe()
824 mvpwm->regs = mvchip->regs; in mvebu_pwm_probe()
826 switch (mvchip->offset) { in mvebu_pwm_probe()
862 regmap_write(mvchip->regs, in mvebu_pwm_probe()
863 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set); in mvebu_pwm_probe()
865 mvpwm->clk_rate = clk_get_rate(mvchip->clk); in mvebu_pwm_probe()
873 mvpwm->chip.npwm = mvchip->chip.ngpio; in mvebu_pwm_probe()
885 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); in mvebu_gpio_dbg_show() local
890 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out); in mvebu_gpio_dbg_show()
891 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf); in mvebu_gpio_dbg_show()
892 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink); in mvebu_gpio_dbg_show()
893 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol); in mvebu_gpio_dbg_show()
894 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); in mvebu_gpio_dbg_show()
895 cause = mvebu_gpio_read_edge_cause(mvchip); in mvebu_gpio_dbg_show()
896 edg_msk = mvebu_gpio_read_edge_mask(mvchip); in mvebu_gpio_dbg_show()
897 lvl_msk = mvebu_gpio_read_level_mask(mvchip); in mvebu_gpio_dbg_show()
961 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); in mvebu_gpio_suspend() local
964 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, in mvebu_gpio_suspend()
965 &mvchip->out_reg); in mvebu_gpio_suspend()
966 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_suspend()
967 &mvchip->io_conf_reg); in mvebu_gpio_suspend()
968 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, in mvebu_gpio_suspend()
969 &mvchip->blink_en_reg); in mvebu_gpio_suspend()
970 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_suspend()
971 &mvchip->in_pol_reg); in mvebu_gpio_suspend()
973 switch (mvchip->soc_variant) { in mvebu_gpio_suspend()
976 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, in mvebu_gpio_suspend()
977 &mvchip->edge_mask_regs[0]); in mvebu_gpio_suspend()
978 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, in mvebu_gpio_suspend()
979 &mvchip->level_mask_regs[0]); in mvebu_gpio_suspend()
983 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
985 &mvchip->edge_mask_regs[i]); in mvebu_gpio_suspend()
986 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
988 &mvchip->level_mask_regs[i]); in mvebu_gpio_suspend()
993 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
995 &mvchip->edge_mask_regs[i]); in mvebu_gpio_suspend()
996 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
998 &mvchip->level_mask_regs[i]); in mvebu_gpio_suspend()
1006 mvebu_pwm_suspend(mvchip); in mvebu_gpio_suspend()
1013 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); in mvebu_gpio_resume() local
1016 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, in mvebu_gpio_resume()
1017 mvchip->out_reg); in mvebu_gpio_resume()
1018 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_resume()
1019 mvchip->io_conf_reg); in mvebu_gpio_resume()
1020 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, in mvebu_gpio_resume()
1021 mvchip->blink_en_reg); in mvebu_gpio_resume()
1022 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_resume()
1023 mvchip->in_pol_reg); in mvebu_gpio_resume()
1025 switch (mvchip->soc_variant) { in mvebu_gpio_resume()
1028 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, in mvebu_gpio_resume()
1029 mvchip->edge_mask_regs[0]); in mvebu_gpio_resume()
1030 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, in mvebu_gpio_resume()
1031 mvchip->level_mask_regs[0]); in mvebu_gpio_resume()
1035 regmap_write(mvchip->regs, in mvebu_gpio_resume()
1037 mvchip->edge_mask_regs[i]); in mvebu_gpio_resume()
1038 regmap_write(mvchip->regs, in mvebu_gpio_resume()
1040 mvchip->level_mask_regs[i]); in mvebu_gpio_resume()
1045 regmap_write(mvchip->regs, in mvebu_gpio_resume()
1047 mvchip->edge_mask_regs[i]); in mvebu_gpio_resume()
1048 regmap_write(mvchip->regs, in mvebu_gpio_resume()
1050 mvchip->level_mask_regs[i]); in mvebu_gpio_resume()
1058 mvebu_pwm_resume(mvchip); in mvebu_gpio_resume()
1064 struct mvebu_gpio_chip *mvchip) in mvebu_gpio_probe_raw() argument
1072 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base, in mvebu_gpio_probe_raw()
1074 if (IS_ERR(mvchip->regs)) in mvebu_gpio_probe_raw()
1075 return PTR_ERR(mvchip->regs); in mvebu_gpio_probe_raw()
1081 mvchip->offset = 0; in mvebu_gpio_probe_raw()
1087 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { in mvebu_gpio_probe_raw()
1092 mvchip->percpu_regs = in mvebu_gpio_probe_raw()
1095 if (IS_ERR(mvchip->percpu_regs)) in mvebu_gpio_probe_raw()
1096 return PTR_ERR(mvchip->percpu_regs); in mvebu_gpio_probe_raw()
1103 struct mvebu_gpio_chip *mvchip) in mvebu_gpio_probe_syscon() argument
1105 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node); in mvebu_gpio_probe_syscon()
1106 if (IS_ERR(mvchip->regs)) in mvebu_gpio_probe_syscon()
1107 return PTR_ERR(mvchip->regs); in mvebu_gpio_probe_syscon()
1109 if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset)) in mvebu_gpio_probe_syscon()
1124 struct mvebu_gpio_chip *mvchip; in mvebu_gpio_probe() local
1148 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), in mvebu_gpio_probe()
1150 if (!mvchip) in mvebu_gpio_probe()
1153 platform_set_drvdata(pdev, mvchip); in mvebu_gpio_probe()
1166 mvchip->clk = devm_clk_get(&pdev->dev, NULL); in mvebu_gpio_probe()
1168 if (!IS_ERR(mvchip->clk)) in mvebu_gpio_probe()
1169 clk_prepare_enable(mvchip->clk); in mvebu_gpio_probe()
1171 mvchip->soc_variant = soc_variant; in mvebu_gpio_probe()
1172 mvchip->chip.label = dev_name(&pdev->dev); in mvebu_gpio_probe()
1173 mvchip->chip.parent = &pdev->dev; in mvebu_gpio_probe()
1174 mvchip->chip.request = gpiochip_generic_request; in mvebu_gpio_probe()
1175 mvchip->chip.free = gpiochip_generic_free; in mvebu_gpio_probe()
1176 mvchip->chip.get_direction = mvebu_gpio_get_direction; in mvebu_gpio_probe()
1177 mvchip->chip.direction_input = mvebu_gpio_direction_input; in mvebu_gpio_probe()
1178 mvchip->chip.get = mvebu_gpio_get; in mvebu_gpio_probe()
1179 mvchip->chip.direction_output = mvebu_gpio_direction_output; in mvebu_gpio_probe()
1180 mvchip->chip.set = mvebu_gpio_set; in mvebu_gpio_probe()
1182 mvchip->chip.to_irq = mvebu_gpio_to_irq; in mvebu_gpio_probe()
1183 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; in mvebu_gpio_probe()
1184 mvchip->chip.ngpio = ngpios; in mvebu_gpio_probe()
1185 mvchip->chip.can_sleep = false; in mvebu_gpio_probe()
1186 mvchip->chip.dbg_show = mvebu_gpio_dbg_show; in mvebu_gpio_probe()
1189 err = mvebu_gpio_probe_syscon(pdev, mvchip); in mvebu_gpio_probe()
1191 err = mvebu_gpio_probe_raw(pdev, mvchip); in mvebu_gpio_probe()
1202 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1203 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0); in mvebu_gpio_probe()
1204 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1205 GPIO_EDGE_MASK_OFF + mvchip->offset, 0); in mvebu_gpio_probe()
1206 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1207 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0); in mvebu_gpio_probe()
1210 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); in mvebu_gpio_probe()
1212 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1214 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1219 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); in mvebu_gpio_probe()
1220 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0); in mvebu_gpio_probe()
1221 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0); in mvebu_gpio_probe()
1223 regmap_write(mvchip->percpu_regs, in mvebu_gpio_probe()
1225 regmap_write(mvchip->percpu_regs, in mvebu_gpio_probe()
1227 regmap_write(mvchip->percpu_regs, in mvebu_gpio_probe()
1235 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip); in mvebu_gpio_probe()
1239 err = mvebu_pwm_probe(pdev, mvchip, id); in mvebu_gpio_probe()
1248 mvchip->domain = in mvebu_gpio_probe()
1250 if (!mvchip->domain) { in mvebu_gpio_probe()
1252 mvchip->chip.label); in mvebu_gpio_probe()
1257 mvchip->domain); in mvebu_gpio_probe()
1262 mvchip->domain, ngpios, 2, np->name, handle_level_irq, in mvebu_gpio_probe()
1266 mvchip->chip.label); in mvebu_gpio_probe()
1274 gc = irq_get_domain_generic_chip(mvchip->domain, 0); in mvebu_gpio_probe()
1275 gc->private = mvchip; in mvebu_gpio_probe()
1281 ct->chip.name = mvchip->chip.label; in mvebu_gpio_probe()
1290 ct->chip.name = mvchip->chip.label; in mvebu_gpio_probe()
1303 mvchip); in mvebu_gpio_probe()