61 	struct hlwd_gpio *hlwd =  in hlwd_gpio_irqhandler()  local
69 	raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);  in hlwd_gpio_irqhandler()
70 	pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG);  in hlwd_gpio_irqhandler()
71 	pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK);  in hlwd_gpio_irqhandler()
74 	emulated_pending = hlwd->edge_emulation & pending;  in hlwd_gpio_irqhandler()
79 		level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);  in hlwd_gpio_irqhandler()
85 			    hlwd->regs + HW_GPIOB_INTLVL);  in hlwd_gpio_irqhandler()
88 		iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG);  in hlwd_gpio_irqhandler()
91 		rising &= hlwd->rising_edge;  in hlwd_gpio_irqhandler()
92 		falling &= hlwd->falling_edge;  in hlwd_gpio_irqhandler()
97 	raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);  in hlwd_gpio_irqhandler()
102 		generic_handle_domain_irq(hlwd->gpioc.irq.domain, hwirq);  in hlwd_gpio_irqhandler()
109 	struct hlwd_gpio *hlwd =  in hlwd_gpio_irq_ack()  local
112 	iowrite32be(BIT(data->hwirq), hlwd->regs + HW_GPIOB_INTFLAG);  in hlwd_gpio_irq_ack()
117 	struct hlwd_gpio *hlwd =  in hlwd_gpio_irq_mask()  local
122 	raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);  in hlwd_gpio_irq_mask()
123 	mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);  in hlwd_gpio_irq_mask()
125 	iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);  in hlwd_gpio_irq_mask()
126 	raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);  in hlwd_gpio_irq_mask()
127 	gpiochip_disable_irq(&hlwd->gpioc, irqd_to_hwirq(data));  in hlwd_gpio_irq_mask()
132 	struct hlwd_gpio *hlwd =  in hlwd_gpio_irq_unmask()  local
137 	gpiochip_enable_irq(&hlwd->gpioc, irqd_to_hwirq(data));  in hlwd_gpio_irq_unmask()
138 	raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);  in hlwd_gpio_irq_unmask()
139 	mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);  in hlwd_gpio_irq_unmask()
141 	iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);  in hlwd_gpio_irq_unmask()
142 	raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);  in hlwd_gpio_irq_unmask()
151 static void hlwd_gpio_irq_setup_emulation(struct hlwd_gpio *hlwd, int hwirq,  in hlwd_gpio_irq_setup_emulation()  argument
157 	level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);  in hlwd_gpio_irq_setup_emulation()
158 	state = ioread32be(hlwd->regs + HW_GPIOB_IN) & BIT(hwirq);  in hlwd_gpio_irq_setup_emulation()
161 	iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);  in hlwd_gpio_irq_setup_emulation()
163 	hlwd->edge_emulation |= BIT(hwirq);  in hlwd_gpio_irq_setup_emulation()
164 	hlwd->rising_edge &= ~BIT(hwirq);  in hlwd_gpio_irq_setup_emulation()
165 	hlwd->falling_edge &= ~BIT(hwirq);  in hlwd_gpio_irq_setup_emulation()
167 		hlwd->rising_edge |= BIT(hwirq);  in hlwd_gpio_irq_setup_emulation()
169 		hlwd->falling_edge |= BIT(hwirq);  in hlwd_gpio_irq_setup_emulation()
174 	struct hlwd_gpio *hlwd =  in hlwd_gpio_irq_set_type()  local
179 	raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);  in hlwd_gpio_irq_set_type()
181 	hlwd->edge_emulation &= ~BIT(data->hwirq);  in hlwd_gpio_irq_set_type()
185 		level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);  in hlwd_gpio_irq_set_type()
187 		iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);  in hlwd_gpio_irq_set_type()
190 		level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);  in hlwd_gpio_irq_set_type()
192 		iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);  in hlwd_gpio_irq_set_type()
197 		hlwd_gpio_irq_setup_emulation(hlwd, data->hwirq, flow_type);  in hlwd_gpio_irq_set_type()
200 		raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);  in hlwd_gpio_irq_set_type()
204 	raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);  in hlwd_gpio_irq_set_type()
210 	struct hlwd_gpio *hlwd =  in hlwd_gpio_irq_print_chip()  local
213 	seq_printf(p, dev_name(hlwd->dev));  in hlwd_gpio_irq_print_chip()
228 	struct hlwd_gpio *hlwd;  in hlwd_gpio_probe()  local
232 	hlwd = devm_kzalloc(&pdev->dev, sizeof(*hlwd), GFP_KERNEL);  in hlwd_gpio_probe()
233 	if (!hlwd)  in hlwd_gpio_probe()
236 	hlwd->regs = devm_platform_ioremap_resource(pdev, 0);  in hlwd_gpio_probe()
237 	if (IS_ERR(hlwd->regs))  in hlwd_gpio_probe()
238 		return PTR_ERR(hlwd->regs);  in hlwd_gpio_probe()
240 	hlwd->dev = &pdev->dev;  in hlwd_gpio_probe()
251 	iowrite32be(0xffffffff, hlwd->regs + HW_GPIO_OWNER);  in hlwd_gpio_probe()
253 	res = bgpio_init(&hlwd->gpioc, &pdev->dev, 4,  in hlwd_gpio_probe()
254 			hlwd->regs + HW_GPIOB_IN, hlwd->regs + HW_GPIOB_OUT,  in hlwd_gpio_probe()
255 			NULL, hlwd->regs + HW_GPIOB_DIR, NULL,  in hlwd_gpio_probe()
265 	hlwd->gpioc.ngpio = ngpios;  in hlwd_gpio_probe()
268 	iowrite32be(0, hlwd->regs + HW_GPIOB_INTMASK);  in hlwd_gpio_probe()
269 	iowrite32be(0xffffffff, hlwd->regs + HW_GPIOB_INTFLAG);  in hlwd_gpio_probe()
278 		hlwd->irq = platform_get_irq(pdev, 0);  in hlwd_gpio_probe()
279 		if (hlwd->irq < 0) {  in hlwd_gpio_probe()
281 				 hlwd->irq);  in hlwd_gpio_probe()
282 			return hlwd->irq;  in hlwd_gpio_probe()
285 		girq = &hlwd->gpioc.irq;  in hlwd_gpio_probe()
294 		girq->parents[0] = hlwd->irq;  in hlwd_gpio_probe()
299 	return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc, hlwd);  in hlwd_gpio_probe()