Lines Matching refs:gpio
105 struct dwapb_gpio *gpio; member
112 (container_of(_gc, struct dwapb_gpio_port, gc)->gpio)
142 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset) in gpio_reg_convert() argument
144 if ((gpio->flags & GPIO_REG_OFFSET_MASK) == GPIO_REG_OFFSET_V2) in gpio_reg_convert()
150 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset) in dwapb_read() argument
152 struct gpio_chip *gc = &gpio->ports[0].gc; in dwapb_read()
153 void __iomem *reg_base = gpio->regs; in dwapb_read()
155 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset)); in dwapb_read()
158 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset, in dwapb_write() argument
161 struct gpio_chip *gc = &gpio->ports[0].gc; in dwapb_write()
162 void __iomem *reg_base = gpio->regs; in dwapb_write()
164 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val); in dwapb_write()
167 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs) in dwapb_offs_to_port() argument
172 for (i = 0; i < gpio->nr_ports; i++) { in dwapb_offs_to_port()
173 port = &gpio->ports[i]; in dwapb_offs_to_port()
181 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs) in dwapb_toggle_trigger() argument
183 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs); in dwapb_toggle_trigger()
192 pol = dwapb_read(gpio, GPIO_INT_POLARITY); in dwapb_toggle_trigger()
200 dwapb_write(gpio, GPIO_INT_POLARITY, pol); in dwapb_toggle_trigger()
203 static u32 dwapb_do_irq(struct dwapb_gpio *gpio) in dwapb_do_irq() argument
205 struct gpio_chip *gc = &gpio->ports[0].gc; in dwapb_do_irq()
209 irq_status = dwapb_read(gpio, GPIO_INTSTATUS); in dwapb_do_irq()
217 dwapb_toggle_trigger(gpio, hwirq); in dwapb_do_irq()
225 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc); in dwapb_irq_handler() local
229 dwapb_do_irq(gpio); in dwapb_irq_handler()
241 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); in dwapb_irq_ack() local
246 dwapb_write(gpio, GPIO_PORTA_EOI, val); in dwapb_irq_ack()
253 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); in dwapb_irq_mask() local
259 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq); in dwapb_irq_mask()
260 dwapb_write(gpio, GPIO_INTMASK, val); in dwapb_irq_mask()
269 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); in dwapb_irq_unmask() local
277 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq); in dwapb_irq_unmask()
278 dwapb_write(gpio, GPIO_INTMASK, val); in dwapb_irq_unmask()
285 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); in dwapb_irq_enable() local
291 val = dwapb_read(gpio, GPIO_INTEN) | BIT(hwirq); in dwapb_irq_enable()
292 dwapb_write(gpio, GPIO_INTEN, val); in dwapb_irq_enable()
293 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq); in dwapb_irq_enable()
294 dwapb_write(gpio, GPIO_INTMASK, val); in dwapb_irq_enable()
301 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); in dwapb_irq_disable() local
307 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq); in dwapb_irq_disable()
308 dwapb_write(gpio, GPIO_INTMASK, val); in dwapb_irq_disable()
309 val = dwapb_read(gpio, GPIO_INTEN) & ~BIT(hwirq); in dwapb_irq_disable()
310 dwapb_write(gpio, GPIO_INTEN, val); in dwapb_irq_disable()
317 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); in dwapb_irq_set_type() local
322 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); in dwapb_irq_set_type()
323 polarity = dwapb_read(gpio, GPIO_INT_POLARITY); in dwapb_irq_set_type()
328 dwapb_toggle_trigger(gpio, bit); in dwapb_irq_set_type()
353 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level); in dwapb_irq_set_type()
355 dwapb_write(gpio, GPIO_INT_POLARITY, polarity); in dwapb_irq_set_type()
365 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); in dwapb_irq_set_wake() local
366 struct dwapb_context *ctx = gpio->ports[0].ctx; in dwapb_irq_set_wake()
397 struct dwapb_gpio *gpio = port->gpio; in dwapb_gpio_set_debounce() local
403 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); in dwapb_gpio_set_debounce()
408 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb); in dwapb_gpio_set_debounce()
443 static void dwapb_configure_irqs(struct dwapb_gpio *gpio, in dwapb_configure_irqs() argument
452 pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL); in dwapb_configure_irqs()
457 dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx); in dwapb_configure_irqs()
473 if (has_acpi_companion(gpio->dev)) { in dwapb_configure_irqs()
478 err = devm_request_irq(gpio->dev, pp->irq[0], in dwapb_configure_irqs()
480 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio); in dwapb_configure_irqs()
482 dev_err(gpio->dev, "error requesting IRQ\n"); in dwapb_configure_irqs()
488 girq->parent_handler_data = gpio; in dwapb_configure_irqs()
497 devm_kfree(gpio->dev, pirq); in dwapb_configure_irqs()
500 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio, in dwapb_gpio_add_port() argument
508 port = &gpio->ports[offs]; in dwapb_gpio_add_port()
509 port->gpio = gpio; in dwapb_gpio_add_port()
513 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL); in dwapb_gpio_add_port()
518 dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE; in dwapb_gpio_add_port()
519 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE; in dwapb_gpio_add_port()
520 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE; in dwapb_gpio_add_port()
523 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout, in dwapb_gpio_add_port()
526 dev_err(gpio->dev, "failed to init gpio chip for port%d\n", in dwapb_gpio_add_port()
541 dwapb_configure_irqs(gpio, port, pp); in dwapb_gpio_add_port()
543 err = devm_gpiochip_add_data(gpio->dev, &port->gc, port); in dwapb_gpio_add_port()
545 dev_err(gpio->dev, "failed to register gpiochip for port%d\n", in dwapb_gpio_add_port()
630 struct dwapb_gpio *gpio = data; in dwapb_assert_reset() local
632 reset_control_assert(gpio->rst); in dwapb_assert_reset()
635 static int dwapb_get_reset(struct dwapb_gpio *gpio) in dwapb_get_reset() argument
639 gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL); in dwapb_get_reset()
640 if (IS_ERR(gpio->rst)) in dwapb_get_reset()
641 return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst), in dwapb_get_reset()
644 err = reset_control_deassert(gpio->rst); in dwapb_get_reset()
646 dev_err(gpio->dev, "Cannot deassert reset lane\n"); in dwapb_get_reset()
650 return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio); in dwapb_get_reset()
655 struct dwapb_gpio *gpio = data; in dwapb_disable_clks() local
657 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks); in dwapb_disable_clks()
660 static int dwapb_get_clks(struct dwapb_gpio *gpio) in dwapb_get_clks() argument
665 gpio->clks[0].id = "bus"; in dwapb_get_clks()
666 gpio->clks[1].id = "db"; in dwapb_get_clks()
667 err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS, in dwapb_get_clks()
668 gpio->clks); in dwapb_get_clks()
670 return dev_err_probe(gpio->dev, err, in dwapb_get_clks()
673 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks); in dwapb_get_clks()
675 dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n"); in dwapb_get_clks()
679 return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio); in dwapb_get_clks()
700 struct dwapb_gpio *gpio; in dwapb_gpio_probe() local
709 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); in dwapb_gpio_probe()
710 if (!gpio) in dwapb_gpio_probe()
713 gpio->dev = &pdev->dev; in dwapb_gpio_probe()
714 gpio->nr_ports = pdata->nports; in dwapb_gpio_probe()
716 err = dwapb_get_reset(gpio); in dwapb_gpio_probe()
720 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports, in dwapb_gpio_probe()
721 sizeof(*gpio->ports), GFP_KERNEL); in dwapb_gpio_probe()
722 if (!gpio->ports) in dwapb_gpio_probe()
725 gpio->regs = devm_platform_ioremap_resource(pdev, 0); in dwapb_gpio_probe()
726 if (IS_ERR(gpio->regs)) in dwapb_gpio_probe()
727 return PTR_ERR(gpio->regs); in dwapb_gpio_probe()
729 err = dwapb_get_clks(gpio); in dwapb_gpio_probe()
733 gpio->flags = (uintptr_t)device_get_match_data(dev); in dwapb_gpio_probe()
735 for (i = 0; i < gpio->nr_ports; i++) { in dwapb_gpio_probe()
736 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i); in dwapb_gpio_probe()
741 platform_set_drvdata(pdev, gpio); in dwapb_gpio_probe()
749 struct dwapb_gpio *gpio = dev_get_drvdata(dev); in dwapb_gpio_suspend() local
750 struct gpio_chip *gc = &gpio->ports[0].gc; in dwapb_gpio_suspend()
755 for (i = 0; i < gpio->nr_ports; i++) { in dwapb_gpio_suspend()
757 unsigned int idx = gpio->ports[i].idx; in dwapb_gpio_suspend()
758 struct dwapb_context *ctx = gpio->ports[i].ctx; in dwapb_gpio_suspend()
761 ctx->dir = dwapb_read(gpio, offset); in dwapb_gpio_suspend()
764 ctx->data = dwapb_read(gpio, offset); in dwapb_gpio_suspend()
767 ctx->ext = dwapb_read(gpio, offset); in dwapb_gpio_suspend()
771 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK); in dwapb_gpio_suspend()
772 ctx->int_en = dwapb_read(gpio, GPIO_INTEN); in dwapb_gpio_suspend()
773 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY); in dwapb_gpio_suspend()
774 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); in dwapb_gpio_suspend()
775 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); in dwapb_gpio_suspend()
778 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en); in dwapb_gpio_suspend()
783 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks); in dwapb_gpio_suspend()
790 struct dwapb_gpio *gpio = dev_get_drvdata(dev); in dwapb_gpio_resume() local
791 struct gpio_chip *gc = &gpio->ports[0].gc; in dwapb_gpio_resume()
795 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks); in dwapb_gpio_resume()
797 dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n"); in dwapb_gpio_resume()
802 for (i = 0; i < gpio->nr_ports; i++) { in dwapb_gpio_resume()
804 unsigned int idx = gpio->ports[i].idx; in dwapb_gpio_resume()
805 struct dwapb_context *ctx = gpio->ports[i].ctx; in dwapb_gpio_resume()
808 dwapb_write(gpio, offset, ctx->data); in dwapb_gpio_resume()
811 dwapb_write(gpio, offset, ctx->dir); in dwapb_gpio_resume()
814 dwapb_write(gpio, offset, ctx->ext); in dwapb_gpio_resume()
818 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type); in dwapb_gpio_resume()
819 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol); in dwapb_gpio_resume()
820 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb); in dwapb_gpio_resume()
821 dwapb_write(gpio, GPIO_INTEN, ctx->int_en); in dwapb_gpio_resume()
822 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask); in dwapb_gpio_resume()
825 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff); in dwapb_gpio_resume()