Lines Matching +full:debounce +full:- +full:ms
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Author: Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>
6 * Copyright (C) 2012-2014 Broadcom Corporation
25 #define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
106 struct bcm_kona_gpio_bank *bank = &kona_gpio->banks[bank_id]; in bcm_kona_gpio_lock_gpio()
108 if (bank->gpio_unlock_count[bit] == 0) { in bcm_kona_gpio_lock_gpio()
109 dev_err(kona_gpio->gpio_chip.parent, in bcm_kona_gpio_lock_gpio()
114 if (--bank->gpio_unlock_count[bit] == 0) { in bcm_kona_gpio_lock_gpio()
115 raw_spin_lock_irqsave(&kona_gpio->lock, flags); in bcm_kona_gpio_lock_gpio()
117 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_lock_gpio()
119 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); in bcm_kona_gpio_lock_gpio()
121 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); in bcm_kona_gpio_lock_gpio()
132 struct bcm_kona_gpio_bank *bank = &kona_gpio->banks[bank_id]; in bcm_kona_gpio_unlock_gpio()
134 if (bank->gpio_unlock_count[bit] == 0) { in bcm_kona_gpio_unlock_gpio()
135 raw_spin_lock_irqsave(&kona_gpio->lock, flags); in bcm_kona_gpio_unlock_gpio()
137 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_unlock_gpio()
139 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); in bcm_kona_gpio_unlock_gpio()
141 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); in bcm_kona_gpio_unlock_gpio()
144 ++bank->gpio_unlock_count[bit]; in bcm_kona_gpio_unlock_gpio()
150 void __iomem *reg_base = kona_gpio->reg_base; in bcm_kona_gpio_get_dir()
167 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_set()
168 raw_spin_lock_irqsave(&kona_gpio->lock, flags); in bcm_kona_gpio_set()
181 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); in bcm_kona_gpio_set()
194 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_get()
195 raw_spin_lock_irqsave(&kona_gpio->lock, flags); in bcm_kona_gpio_get()
205 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); in bcm_kona_gpio_get()
234 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_direction_input()
235 raw_spin_lock_irqsave(&kona_gpio->lock, flags); in bcm_kona_gpio_direction_input()
242 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); in bcm_kona_gpio_direction_input()
258 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_direction_output()
259 raw_spin_lock_irqsave(&kona_gpio->lock, flags); in bcm_kona_gpio_direction_output()
271 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); in bcm_kona_gpio_direction_output()
281 if (gpio >= kona_gpio->gpio_chip.ngpio) in bcm_kona_gpio_to_irq()
282 return -ENXIO; in bcm_kona_gpio_to_irq()
283 return irq_create_mapping(kona_gpio->irq_domain, gpio); in bcm_kona_gpio_to_irq()
287 unsigned debounce) in bcm_kona_gpio_set_debounce() argument
295 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_set_debounce()
296 /* debounce must be 1-128ms (or 0) */ in bcm_kona_gpio_set_debounce()
297 if ((debounce > 0 && debounce < 1000) || debounce > 128000) { in bcm_kona_gpio_set_debounce()
298 dev_err(chip->parent, "Debounce value %u not in range\n", in bcm_kona_gpio_set_debounce()
299 debounce); in bcm_kona_gpio_set_debounce()
300 return -EINVAL; in bcm_kona_gpio_set_debounce()
303 /* calculate debounce bit value */ in bcm_kona_gpio_set_debounce()
304 if (debounce != 0) { in bcm_kona_gpio_set_debounce()
305 /* Convert to ms */ in bcm_kona_gpio_set_debounce()
306 debounce /= 1000; in bcm_kona_gpio_set_debounce()
308 res = fls(debounce) - 1; in bcm_kona_gpio_set_debounce()
309 /* Check if MSB-1 is set (round up or down) */ in bcm_kona_gpio_set_debounce()
310 if (res > 0 && (debounce & BIT(res - 1))) in bcm_kona_gpio_set_debounce()
314 /* spin lock for read-modify-write of the GPIO register */ in bcm_kona_gpio_set_debounce()
315 raw_spin_lock_irqsave(&kona_gpio->lock, flags); in bcm_kona_gpio_set_debounce()
320 if (debounce == 0) { in bcm_kona_gpio_set_debounce()
321 /* disable debounce */ in bcm_kona_gpio_set_debounce()
330 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); in bcm_kona_gpio_set_debounce()
338 u32 debounce; in bcm_kona_gpio_set_config() local
341 return -ENOTSUPP; in bcm_kona_gpio_set_config()
343 debounce = pinconf_to_config_argument(config); in bcm_kona_gpio_set_config()
344 return bcm_kona_gpio_set_debounce(chip, gpio, debounce); in bcm_kona_gpio_set_config()
348 .label = "bcm-kona-gpio",
366 unsigned gpio = d->hwirq; in bcm_kona_gpio_irq_ack()
373 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_irq_ack()
374 raw_spin_lock_irqsave(&kona_gpio->lock, flags); in bcm_kona_gpio_irq_ack()
380 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); in bcm_kona_gpio_irq_ack()
387 unsigned gpio = d->hwirq; in bcm_kona_gpio_irq_mask()
394 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_irq_mask()
396 raw_spin_lock_irqsave(&kona_gpio->lock, flags); in bcm_kona_gpio_irq_mask()
401 gpiochip_disable_irq(&kona_gpio->gpio_chip, gpio); in bcm_kona_gpio_irq_mask()
403 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); in bcm_kona_gpio_irq_mask()
410 unsigned gpio = d->hwirq; in bcm_kona_gpio_irq_unmask()
417 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_irq_unmask()
419 raw_spin_lock_irqsave(&kona_gpio->lock, flags); in bcm_kona_gpio_irq_unmask()
424 gpiochip_enable_irq(&kona_gpio->gpio_chip, gpio); in bcm_kona_gpio_irq_unmask()
426 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); in bcm_kona_gpio_irq_unmask()
433 unsigned gpio = d->hwirq; in bcm_kona_gpio_irq_set_type()
439 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_irq_set_type()
457 dev_err(kona_gpio->gpio_chip.parent, in bcm_kona_gpio_irq_set_type()
459 return -EINVAL; in bcm_kona_gpio_irq_set_type()
462 raw_spin_lock_irqsave(&kona_gpio->lock, flags); in bcm_kona_gpio_irq_set_type()
469 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); in bcm_kona_gpio_irq_set_type()
489 reg_base = bank->kona_gpio->reg_base; in bcm_kona_gpio_irq_handler()
490 bank_id = bank->id; in bcm_kona_gpio_irq_handler()
503 generic_handle_domain_irq(bank->kona_gpio->irq_domain, in bcm_kona_gpio_irq_handler()
514 unsigned int gpio = d->hwirq; in bcm_kona_gpio_irq_reqres()
522 return gpiochip_reqres_irq(&kona_gpio->gpio_chip, gpio); in bcm_kona_gpio_irq_reqres()
528 unsigned int gpio = d->hwirq; in bcm_kona_gpio_irq_relres()
533 gpiochip_relres_irq(&kona_gpio->gpio_chip, gpio); in bcm_kona_gpio_irq_relres()
537 .name = "bcm-kona-gpio",
547 { .compatible = "brcm,kona-gpio" },
563 ret = irq_set_chip_data(irq, d->host_data); in bcm_kona_gpio_irq_map()
590 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_reset()
592 for (i = 0; i < kona_gpio->num_bank; i++) { in bcm_kona_gpio_reset()
597 /* Now re-lock the bank */ in bcm_kona_gpio_reset()
604 struct device *dev = &pdev->dev; in bcm_kona_gpio_probe()
613 return -ENOMEM; in bcm_kona_gpio_probe()
615 kona_gpio->gpio_chip = template_chip; in bcm_kona_gpio_probe()
616 chip = &kona_gpio->gpio_chip; in bcm_kona_gpio_probe()
620 return -ENOENT; in bcm_kona_gpio_probe()
624 kona_gpio->num_bank = ret; in bcm_kona_gpio_probe()
626 if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) { in bcm_kona_gpio_probe()
629 return -ENXIO; in bcm_kona_gpio_probe()
631 kona_gpio->banks = devm_kcalloc(dev, in bcm_kona_gpio_probe()
632 kona_gpio->num_bank, in bcm_kona_gpio_probe()
633 sizeof(*kona_gpio->banks), in bcm_kona_gpio_probe()
635 if (!kona_gpio->banks) in bcm_kona_gpio_probe()
636 return -ENOMEM; in bcm_kona_gpio_probe()
638 chip->parent = dev; in bcm_kona_gpio_probe()
639 chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK; in bcm_kona_gpio_probe()
641 kona_gpio->irq_domain = irq_domain_create_linear(dev_fwnode(dev), in bcm_kona_gpio_probe()
642 chip->ngpio, in bcm_kona_gpio_probe()
645 if (!kona_gpio->irq_domain) { in bcm_kona_gpio_probe()
647 return -ENXIO; in bcm_kona_gpio_probe()
650 kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0); in bcm_kona_gpio_probe()
651 if (IS_ERR(kona_gpio->reg_base)) { in bcm_kona_gpio_probe()
652 ret = PTR_ERR(kona_gpio->reg_base); in bcm_kona_gpio_probe()
656 for (i = 0; i < kona_gpio->num_bank; i++) { in bcm_kona_gpio_probe()
657 bank = &kona_gpio->banks[i]; in bcm_kona_gpio_probe()
658 bank->id = i; in bcm_kona_gpio_probe()
659 bank->irq = platform_get_irq(pdev, i); in bcm_kona_gpio_probe()
660 bank->kona_gpio = kona_gpio; in bcm_kona_gpio_probe()
661 if (bank->irq < 0) { in bcm_kona_gpio_probe()
663 ret = -ENOENT; in bcm_kona_gpio_probe()
668 dev_info(&pdev->dev, "Setting up Kona GPIO\n"); in bcm_kona_gpio_probe()
674 dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret); in bcm_kona_gpio_probe()
677 for (i = 0; i < kona_gpio->num_bank; i++) { in bcm_kona_gpio_probe()
678 bank = &kona_gpio->banks[i]; in bcm_kona_gpio_probe()
679 irq_set_chained_handler_and_data(bank->irq, in bcm_kona_gpio_probe()
684 raw_spin_lock_init(&kona_gpio->lock); in bcm_kona_gpio_probe()
689 irq_domain_remove(kona_gpio->irq_domain); in bcm_kona_gpio_probe()
696 .name = "bcm-kona-gpio",