269 			dev_err(&mgr->dev,  in zynq_fpga_ops_write_init()
279 			dev_err(&mgr->dev,  in zynq_fpga_ops_write_init()
312 			dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n");  in zynq_fpga_ops_write_init()
326 			dev_err(&mgr->dev, "Timeout waiting for !PCFG_INIT\n");  in zynq_fpga_ops_write_init()
340 			dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n");  in zynq_fpga_ops_write_init()
365 		dev_err(&mgr->dev, "DMA command queue not right\n");  in zynq_fpga_ops_write_init()
402 			dev_err(&mgr->dev,  in zynq_fpga_ops_write()
409 	    dma_map_sg(mgr->dev.parent, sgt->sgl, sgt->nents, DMA_TO_DEVICE);  in zynq_fpga_ops_write()
411 		dev_err(&mgr->dev, "Unable to DMA map (TO_DEVICE)\n");  in zynq_fpga_ops_write()
467 	dev_err(&mgr->dev,  in zynq_fpga_ops_write()
481 	dma_unmap_sg(mgr->dev.parent, sgt->sgl, sgt->nents, DMA_TO_DEVICE);  in zynq_fpga_ops_write()
555 	struct device *dev = &pdev->dev;  in zynq_fpga_probe()  local
560 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);  in zynq_fpga_probe()
569 	priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node,  in zynq_fpga_probe()
572 		dev_err(dev, "unable to get zynq-slcr regmap\n");  in zynq_fpga_probe()
582 	priv->clk = devm_clk_get(dev, "ref_clk");  in zynq_fpga_probe()
584 		return dev_err_probe(dev, PTR_ERR(priv->clk),  in zynq_fpga_probe()
589 		dev_err(dev, "unable to enable clock\n");  in zynq_fpga_probe()
598 	err = devm_request_irq(dev, priv->irq, zynq_fpga_isr, 0, dev_name(dev),  in zynq_fpga_probe()
601 		dev_err(dev, "unable to request IRQ\n");  in zynq_fpga_probe()
608 	mgr = fpga_mgr_register(dev, "Xilinx Zynq FPGA Manager",  in zynq_fpga_probe()
611 		dev_err(dev, "unable to register FPGA manager\n");  in zynq_fpga_probe()