Lines Matching +full:data +full:- +full:clock +full:- +full:ratio
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2016 Altera Corporation
10 #include <linux/fpga/fpga-mgr.h>
54 /* FPGA CD Ratio Value */
65 * struct a10_fpga_priv - private data for fpga manager
67 * @fpga_data_addr: iomap for single address data register to FPGA
68 * @clk: clock
123 regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST, in socfpga_a10_fpga_set_cfg_width()
133 regmap_write(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST, in socfpga_a10_fpga_generate_dclks()
137 regmap_write(priv->regmap, A10_FPGAMGR_DCLKCNT_OFST, count); in socfpga_a10_fpga_generate_dclks()
140 regmap_read_poll_timeout(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST, val, in socfpga_a10_fpga_generate_dclks()
144 regmap_write(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST, in socfpga_a10_fpga_generate_dclks()
154 return -EINVAL; in socfpga_a10_fpga_encrypted()
163 return -EINVAL; in socfpga_a10_fpga_compressed()
175 * cd ratio is dependent on cfg width and whether the bitstream in socfpga_a10_fpga_get_cd_ratio()
178 * | width | encr. | compr. | cd ratio | in socfpga_a10_fpga_get_cd_ratio()
196 /* If 32 bit, double the cd ratio by incrementing the field */ in socfpga_a10_fpga_get_cd_ratio()
207 struct a10_fpga_priv *priv = mgr->priv; in socfpga_a10_fpga_set_cdratio()
213 return -EINVAL; in socfpga_a10_fpga_set_cdratio()
217 return -EINVAL; in socfpga_a10_fpga_set_cdratio()
221 regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST, in socfpga_a10_fpga_set_cdratio()
232 regmap_read(priv->regmap, A10_FPGAMGR_IMGCFG_STAT_OFST, &val); in socfpga_a10_fpga_read_stat()
245 return -EINVAL; in socfpga_a10_fpga_wait_for_pr_ready()
251 return -ETIMEDOUT; in socfpga_a10_fpga_wait_for_pr_ready()
262 return -EINVAL; in socfpga_a10_fpga_wait_for_pr_done()
268 return -ETIMEDOUT; in socfpga_a10_fpga_wait_for_pr_done()
276 struct a10_fpga_priv *priv = mgr->priv; in socfpga_a10_fpga_write_init()
281 if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) in socfpga_a10_fpga_write_init()
284 return -EINVAL; in socfpga_a10_fpga_write_init()
291 dev_dbg(&mgr->dev, "Fail: invalid msel=%d\n", msel); in socfpga_a10_fpga_write_init()
292 return -EINVAL; in socfpga_a10_fpga_write_init()
300 return -EINVAL; in socfpga_a10_fpga_write_init()
305 /* Determine cd ratio from bitstream header and set cd ratio */ in socfpga_a10_fpga_write_init()
314 regmap_write(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST, in socfpga_a10_fpga_write_init()
317 /* Set cfg_ctrl to enable s2f dclk and data */ in socfpga_a10_fpga_write_init()
318 regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST, in socfpga_a10_fpga_write_init()
326 regmap_write(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_00_OFST, in socfpga_a10_fpga_write_init()
332 /* Enable override for data, dclk, nce, and pr_request to CSS */ in socfpga_a10_fpga_write_init()
333 regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST, in socfpga_a10_fpga_write_init()
340 regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST, in socfpga_a10_fpga_write_init()
344 /* Provide 2048 DCLKs before starting the config data streaming. */ in socfpga_a10_fpga_write_init()
352 * write data to the FPGA data register
357 struct a10_fpga_priv *priv = mgr->priv; in socfpga_a10_fpga_write()
362 return -EINVAL; in socfpga_a10_fpga_write()
364 /* Write out the complete 32-bit chunks */ in socfpga_a10_fpga_write()
366 writel(buffer_32[i++], priv->fpga_data_addr); in socfpga_a10_fpga_write()
367 count -= sizeof(u32); in socfpga_a10_fpga_write()
370 /* Write out remaining non 32-bit chunks */ in socfpga_a10_fpga_write()
373 writel(buffer_32[i++] & 0x00ffffff, priv->fpga_data_addr); in socfpga_a10_fpga_write()
376 writel(buffer_32[i++] & 0x0000ffff, priv->fpga_data_addr); in socfpga_a10_fpga_write()
379 writel(buffer_32[i++] & 0x000000ff, priv->fpga_data_addr); in socfpga_a10_fpga_write()
385 return -EFAULT; in socfpga_a10_fpga_write()
394 struct a10_fpga_priv *priv = mgr->priv; in socfpga_a10_fpga_write_complete()
402 regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST, in socfpga_a10_fpga_write_complete()
408 /* Disable s2f dclk and data */ in socfpga_a10_fpga_write_complete()
409 regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST, in socfpga_a10_fpga_write_complete()
413 regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST, in socfpga_a10_fpga_write_complete()
417 /* Disable data, dclk, nce, and pr_request override to CSS */ in socfpga_a10_fpga_write_complete()
418 regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST, in socfpga_a10_fpga_write_complete()
432 dev_dbg(&mgr->dev, in socfpga_a10_fpga_write_complete()
434 return -ETIMEDOUT; in socfpga_a10_fpga_write_complete()
442 struct a10_fpga_priv *priv = mgr->priv; in socfpga_a10_fpga_state()
470 struct device *dev = &pdev->dev; in socfpga_a10_fpga_probe()
478 return -ENOMEM; in socfpga_a10_fpga_probe()
485 /* Second mmio base is for writing FPGA image data */ in socfpga_a10_fpga_probe()
486 priv->fpga_data_addr = devm_platform_ioremap_resource(pdev, 1); in socfpga_a10_fpga_probe()
487 if (IS_ERR(priv->fpga_data_addr)) in socfpga_a10_fpga_probe()
488 return PTR_ERR(priv->fpga_data_addr); in socfpga_a10_fpga_probe()
491 priv->regmap = devm_regmap_init_mmio(dev, reg_base, in socfpga_a10_fpga_probe()
493 if (IS_ERR(priv->regmap)) in socfpga_a10_fpga_probe()
494 return -ENODEV; in socfpga_a10_fpga_probe()
496 priv->clk = devm_clk_get(dev, NULL); in socfpga_a10_fpga_probe()
497 if (IS_ERR(priv->clk)) { in socfpga_a10_fpga_probe()
498 dev_err(dev, "no clock specified\n"); in socfpga_a10_fpga_probe()
499 return PTR_ERR(priv->clk); in socfpga_a10_fpga_probe()
502 ret = clk_prepare_enable(priv->clk); in socfpga_a10_fpga_probe()
504 dev_err(dev, "could not enable clock\n"); in socfpga_a10_fpga_probe()
505 return -EBUSY; in socfpga_a10_fpga_probe()
511 clk_disable_unprepare(priv->clk); in socfpga_a10_fpga_probe()
523 struct a10_fpga_priv *priv = mgr->priv; in socfpga_a10_fpga_remove()
526 clk_disable_unprepare(priv->clk); in socfpga_a10_fpga_remove()
532 { .compatible = "altr,socfpga-a10-fpga-mgr", },