39 			 (unsigned int)FIELD_GET(FME_CAP_NUM_PORTS, v));  in ports_num_show()
90 		       (unsigned int)FIELD_GET(FME_CAP_CACHE_SIZE, v));  in cache_size_show()
105 		       (unsigned int)FIELD_GET(FME_CAP_FABRIC_VERID, v));  in fabric_version_show()
120 		       (unsigned int)FIELD_GET(FME_CAP_SOCKET_ID, v));  in socket_id_show()
210 	return FIELD_GET(THERM_NO_THROTTLE, v) ? false : true;  in fme_thermal_throttle_support()
235 		*val = (long)(FIELD_GET(FPGA_TEMPERATURE, v) * MILLI);  in thermal_hwmon_read()
239 		*val = (long)(FIELD_GET(TEMP_THRESHOLD1, v) * MILLI);  in thermal_hwmon_read()
243 		*val = (long)(FIELD_GET(TEMP_THRESHOLD2, v) * MILLI);  in thermal_hwmon_read()
247 		*val = (long)(FIELD_GET(TRIP_THRESHOLD, v) * MILLI);  in thermal_hwmon_read()
251 		*val = (long)FIELD_GET(TEMP_THRESHOLD1_STATUS, v);  in thermal_hwmon_read()
255 		*val = (long)FIELD_GET(TEMP_THRESHOLD2_STATUS, v);  in thermal_hwmon_read()
290 		       (unsigned int)FIELD_GET(TEMP_THRESHOLD1_POLICY, v));  in temp1_max_policy_show()
386 		*val = (long)(FIELD_GET(PWR_CONSUMED, v) * MICRO);  in power_hwmon_read()
390 		*val = (long)(FIELD_GET(PWR_THRESHOLD1, v) * MICRO);  in power_hwmon_read()
394 		*val = (long)(FIELD_GET(PWR_THRESHOLD2, v) * MICRO);  in power_hwmon_read()
398 		*val = (long)FIELD_GET(PWR_THRESHOLD1_STATUS, v);  in power_hwmon_read()
402 		*val = (long)FIELD_GET(PWR_THRESHOLD2_STATUS, v);  in power_hwmon_read()
490 	if (FIELD_GET(XEON_PWR_EN, v))  in power1_xeon_limit_show()
491 		xeon_limit = FIELD_GET(XEON_PWR_LIMIT, v);  in power1_xeon_limit_show()
505 	if (FIELD_GET(FPGA_PWR_EN, v))  in power1_fpga_limit_show()
506 		fpga_limit = FIELD_GET(FPGA_PWR_LIMIT, v);  in power1_fpga_limit_show()
520 		       (unsigned int)FIELD_GET(FME_LATENCY_TOLERANCE, v));  in power1_ltr_show()