Lines Matching refs:a

112 	  freeze bridge is a bridge that exists in the FPGA fabric to
128 	  safely handles AXI4MM and AXI4-Lite interfaces on a
138 	  and the FPGA Bridges associated with either a reconfigurable
139 	  region of an FPGA or a whole FPGA.
145 	  Support for loading FPGA images by applying a Device Tree
154 	  Device Feature List (DFL) defines a feature list structure that
155 	  creates a linked list of feature headers within the MMIO space
169 	  The FPGA Management Engine (FME) is a feature device implemented
199 	  to the FPGA infrastructure via a Port. There may be more than one
226 	  To compile this as a module, choose M here.
245 	  To compile this as a module, choose M here.
256 	  This is a subdriver of the Intel MAX10 board management controller