Lines Matching refs:tegra_ivc_header_write_field

74 #define tegra_ivc_header_write_field(hdr, field, value) \  macro
151 	tegra_ivc_header_write_field(&ivc->tx.map, tx.count, count + 1);  in tegra_ivc_advance_tx()
163 	tegra_ivc_header_write_field(&ivc->rx.map, rx.count, count + 1);  in tegra_ivc_advance_rx()
402 	tegra_ivc_header_write_field(&ivc->tx.map, tx.state, TEGRA_IVC_STATE_SYNC);  in tegra_ivc_reset()
452 		tegra_ivc_header_write_field(&ivc->tx.map, tx.count, 0);  in tegra_ivc_notified()
453 		tegra_ivc_header_write_field(&ivc->rx.map, rx.count, 0);  in tegra_ivc_notified()
468 		tegra_ivc_header_write_field(&ivc->tx.map, tx.state, TEGRA_IVC_STATE_ACK);  in tegra_ivc_notified()
491 		tegra_ivc_header_write_field(&ivc->tx.map, tx.count, 0);  in tegra_ivc_notified()
492 		tegra_ivc_header_write_field(&ivc->rx.map, rx.count, 0);  in tegra_ivc_notified()
508 		tegra_ivc_header_write_field(&ivc->tx.map, tx.state, TEGRA_IVC_STATE_ESTABLISHED);  in tegra_ivc_notified()
532 		tegra_ivc_header_write_field(&ivc->tx.map, tx.state, TEGRA_IVC_STATE_ESTABLISHED);  in tegra_ivc_notified()