Lines Matching +full:zynqmp +full:- +full:ddrc +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2012 - 2014 Xilinx, Inc.
56 #define CTRL_BW_SHIFT 2
92 #define DDR_ECC_INTR_SELF_CLEAR BIT(2)
94 /* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */
140 #define ECC_CTRL_CLR_CE_ERRCNT BIT(2)
144 #define DDRCTL_EWDTH_16 2
200 /* DDRC Software control register */
203 /* DDRC ECC CE & UE poison mask */
207 /* DDRC Device config masks */
218 #define DDR_MAX_BANKGRP_SHIFT 2
245 #define COL_B2_BASE 2
258 #define BANK_B0_BASE 2
262 #define BANKGRP_B0_BASE 2
268 * struct ecc_error_info - ECC error log information.
288 * struct synps_ecc_status - ECC status information to report.
302 * struct synps_edac_priv - DDR memory controller private instance data.
330 u32 bankgrp_shift[2];
336 * struct synps_platform_data - synps platform data structure.
356 * zynq_get_error_info - Get the current ECC error info.
367 base = priv->baseaddr; in zynq_get_error_info()
368 p = &priv->stat; in zynq_get_error_info()
374 p->ce_cnt = (regval & STAT_CECNT_MASK) >> STAT_CECNT_SHIFT; in zynq_get_error_info()
375 p->ue_cnt = regval & STAT_UECNT_MASK; in zynq_get_error_info()
378 if (!(p->ce_cnt && (regval & LOG_VALID))) in zynq_get_error_info()
381 p->ceinfo.bitpos = (regval & CE_LOG_BITPOS_MASK) >> CE_LOG_BITPOS_SHIFT; in zynq_get_error_info()
383 p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; in zynq_get_error_info()
384 p->ceinfo.col = regval & ADDR_COL_MASK; in zynq_get_error_info()
385 p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; in zynq_get_error_info()
386 p->ceinfo.data = readl(base + CE_DATA_31_0_OFST); in zynq_get_error_info()
387 edac_dbg(3, "CE bit position: %d data: %d\n", p->ceinfo.bitpos, in zynq_get_error_info()
388 p->ceinfo.data); in zynq_get_error_info()
393 if (!(p->ue_cnt && (regval & LOG_VALID))) in zynq_get_error_info()
397 p->ueinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; in zynq_get_error_info()
398 p->ueinfo.col = regval & ADDR_COL_MASK; in zynq_get_error_info()
399 p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; in zynq_get_error_info()
400 p->ueinfo.data = readl(base + UE_DATA_31_0_OFST); in zynq_get_error_info()
412 * zynqmp_get_mem_info - Get the current memory info.
421 linear_addr = priv->poison_addr; in zynqmp_get_mem_info()
423 linear_addr = linear_addr - SZ_32G + SZ_2G; in zynqmp_get_mem_info()
430 * zynqmp_get_error_info - Get the current ECC error info.
442 base = priv->baseaddr; in zynqmp_get_error_info()
443 p = &priv->stat; in zynqmp_get_error_info()
446 p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK; in zynqmp_get_error_info()
447 p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT; in zynqmp_get_error_info()
448 if (!p->ce_cnt) in zynqmp_get_error_info()
455 p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK); in zynqmp_get_error_info()
458 p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK); in zynqmp_get_error_info()
460 p->ceinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> in zynqmp_get_error_info()
462 p->ceinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >> in zynqmp_get_error_info()
464 p->ceinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK); in zynqmp_get_error_info()
465 p->ceinfo.data = readl(base + ECC_CSYND0_OFST); in zynqmp_get_error_info()
466 edac_dbg(2, "ECCCSYN0: 0x%08X ECCCSYN1: 0x%08X ECCCSYN2: 0x%08X\n", in zynqmp_get_error_info()
470 if (!p->ue_cnt) in zynqmp_get_error_info()
474 p->ueinfo.row = (regval & ECC_CEADDR0_RW_MASK); in zynqmp_get_error_info()
476 p->ueinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >> in zynqmp_get_error_info()
478 p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> in zynqmp_get_error_info()
480 p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK); in zynqmp_get_error_info()
481 p->ueinfo.data = readl(base + ECC_UESYND0_OFST); in zynqmp_get_error_info()
483 spin_lock_irqsave(&priv->reglock, flags); in zynqmp_get_error_info()
490 spin_unlock_irqrestore(&priv->reglock, flags); in zynqmp_get_error_info()
496 * handle_error - Handle Correctable and Uncorrectable errors.
504 struct synps_edac_priv *priv = mci->pvt_info; in handle_error()
507 if (p->ce_cnt) { in handle_error()
508 pinf = &p->ceinfo; in handle_error()
509 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in handle_error()
510 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
512 "CE", pinf->row, pinf->bank, in handle_error()
513 pinf->bankgrpnr, pinf->blknr, in handle_error()
514 pinf->bitpos, pinf->data); in handle_error()
516 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
518 "CE", pinf->row, pinf->bank, pinf->col, in handle_error()
519 pinf->bitpos, pinf->data); in handle_error()
523 p->ce_cnt, 0, 0, 0, 0, 0, -1, in handle_error()
524 priv->message, ""); in handle_error()
527 if (p->ue_cnt) { in handle_error()
528 pinf = &p->ueinfo; in handle_error()
529 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in handle_error()
530 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
532 "UE", pinf->row, pinf->bank, in handle_error()
533 pinf->bankgrpnr, pinf->blknr); in handle_error()
535 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
537 "UE", pinf->row, pinf->bank, pinf->col); in handle_error()
541 p->ue_cnt, 0, 0, 0, 0, 0, -1, in handle_error()
542 priv->message, ""); in handle_error()
553 if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) { in enable_intr()
555 priv->baseaddr + DDR_QOS_IRQ_EN_OFST); in enable_intr()
560 spin_lock_irqsave(&priv->reglock, flags); in enable_intr()
563 priv->baseaddr + ECC_CLR_OFST); in enable_intr()
565 spin_unlock_irqrestore(&priv->reglock, flags); in enable_intr()
573 if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) { in disable_intr()
575 priv->baseaddr + DDR_QOS_IRQ_DB_OFST); in disable_intr()
580 spin_lock_irqsave(&priv->reglock, flags); in disable_intr()
582 writel(0, priv->baseaddr + ECC_CLR_OFST); in disable_intr()
584 spin_unlock_irqrestore(&priv->reglock, flags); in disable_intr()
588 * intr_handler - Interrupt Handler for ECC interrupts.
601 priv = mci->pvt_info; in intr_handler()
602 p_data = priv->p_data; in intr_handler()
608 if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) { in intr_handler()
609 regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); in intr_handler()
615 status = p_data->get_error_info(priv); in intr_handler()
619 priv->ce_cnt += priv->stat.ce_cnt; in intr_handler()
620 priv->ue_cnt += priv->stat.ue_cnt; in intr_handler()
621 handle_error(mci, &priv->stat); in intr_handler()
624 priv->ce_cnt, priv->ue_cnt); in intr_handler()
626 if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) in intr_handler()
627 writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); in intr_handler()
633 * check_errors - Check controller for ECC errors.
644 priv = mci->pvt_info; in check_errors()
645 p_data = priv->p_data; in check_errors()
647 status = p_data->get_error_info(priv); in check_errors()
651 priv->ce_cnt += priv->stat.ce_cnt; in check_errors()
652 priv->ue_cnt += priv->stat.ue_cnt; in check_errors()
653 handle_error(mci, &priv->stat); in check_errors()
656 priv->ce_cnt, priv->ue_cnt); in check_errors()
660 * zynq_get_dtype - Return the controller memory width.
691 * zynqmp_get_dtype - Return the controller memory width.
724 * zynq_get_ecc_state - Return the controller ECC enable/disable status.
748 * zynqmp_get_ecc_state - Return the controller ECC enable/disable status.
753 * Return: a ECC status boolean i.e true/false - enabled/disabled.
773 * get_memsize - Read the size of the attached memory device.
787 * zynq_get_mtype - Return the controller memory type.
811 * zynqmp_get_mtype - Returns controller memory type.
839 * init_csrows - Initialize the csrow data.
847 struct synps_edac_priv *priv = mci->pvt_info; in init_csrows()
854 p_data = priv->p_data; in init_csrows()
856 for (row = 0; row < mci->nr_csrows; row++) { in init_csrows()
857 csi = mci->csrows[row]; in init_csrows()
860 for (j = 0; j < csi->nr_channels; j++) { in init_csrows()
861 dimm = csi->channels[j]->dimm; in init_csrows()
862 dimm->edac_mode = EDAC_SECDED; in init_csrows()
863 dimm->mtype = p_data->get_mtype(priv->baseaddr); in init_csrows()
864 dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels; in init_csrows()
865 dimm->grain = SYNPS_EDAC_ERR_GRAIN; in init_csrows()
866 dimm->dtype = p_data->get_dtype(priv->baseaddr); in init_csrows()
872 * mc_init - Initialize one driver instance.
877 * related driver-private data associated with the memory controller the
884 mci->pdev = &pdev->dev; in mc_init()
885 priv = mci->pvt_info; in mc_init()
889 mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2; in mc_init()
890 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; in mc_init()
891 mci->scrub_cap = SCRUB_HW_SRC; in mc_init()
892 mci->scrub_mode = SCRUB_NONE; in mc_init()
894 mci->edac_cap = EDAC_FLAG_SECDED; in mc_init()
895 mci->ctl_name = "synps_ddr_controller"; in mc_init()
896 mci->dev_name = SYNPS_EDAC_MOD_STRING; in mc_init()
897 mci->mod_name = SYNPS_EDAC_MOD_VER; in mc_init()
899 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in mc_init()
903 mci->edac_check = check_errors; in mc_init()
906 mci->ctl_page_to_phys = NULL; in mc_init()
914 struct synps_edac_priv *priv = mci->pvt_info; in setup_irq()
924 ret = devm_request_irq(&pdev->dev, irq, intr_handler, in setup_irq()
925 0, dev_name(&pdev->dev), mci); in setup_irq()
974 .compatible = "xlnx,zynq-ddrc-a05",
978 .compatible = "xlnx,zynqmp-ddrc-2.40a",
982 .compatible = "snps,ddrc-3.80a",
996 * ddr_poison_setup - Update poison registers.
1009 p_data = priv->p_data; in ddr_poison_setup()
1011 if (p_data->get_mem_info) in ddr_poison_setup()
1012 hif_addr = p_data->get_mem_info(priv); in ddr_poison_setup()
1014 hif_addr = priv->poison_addr >> 3; in ddr_poison_setup()
1017 if (priv->row_shift[index]) in ddr_poison_setup()
1018 row |= (((hif_addr >> priv->row_shift[index]) & in ddr_poison_setup()
1025 if (priv->col_shift[index] || index < 3) in ddr_poison_setup()
1026 col |= (((hif_addr >> priv->col_shift[index]) & in ddr_poison_setup()
1033 if (priv->bank_shift[index]) in ddr_poison_setup()
1034 bank |= (((hif_addr >> priv->bank_shift[index]) & in ddr_poison_setup()
1041 if (priv->bankgrp_shift[index]) in ddr_poison_setup()
1042 bankgrp |= (((hif_addr >> priv->bankgrp_shift[index]) in ddr_poison_setup()
1048 if (priv->rank_shift[0]) in ddr_poison_setup()
1049 rank = (hif_addr >> priv->rank_shift[0]) & BIT(0); in ddr_poison_setup()
1053 writel(regval, priv->baseaddr + ECC_POISON0_OFST); in ddr_poison_setup()
1058 writel(regval, priv->baseaddr + ECC_POISON1_OFST); in ddr_poison_setup()
1066 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_error_show()
1070 readl(priv->baseaddr + ECC_POISON0_OFST), in inject_data_error_show()
1071 readl(priv->baseaddr + ECC_POISON1_OFST), in inject_data_error_show()
1072 priv->poison_addr); in inject_data_error_show()
1080 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_error_store()
1082 if (kstrtoul(data, 0, &priv->poison_addr)) in inject_data_error_store()
1083 return -EINVAL; in inject_data_error_store()
1095 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_poison_show()
1098 (((readl(priv->baseaddr + ECC_CFG1_OFST)) & 0x3) == 0x3) in inject_data_poison_show()
1107 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_poison_store()
1109 writel(0, priv->baseaddr + DDRC_SWCTL); in inject_data_poison_store()
1110 if (strncmp(data, "CE", 2) == 0) in inject_data_poison_store()
1111 writel(ECC_CEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST); in inject_data_poison_store()
1113 writel(ECC_UEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST); in inject_data_poison_store()
1114 writel(1, priv->baseaddr + DDRC_SWCTL); in inject_data_poison_store()
1126 rc = device_create_file(&mci->dev, &dev_attr_inject_data_error); in edac_create_sysfs_attributes()
1129 rc = device_create_file(&mci->dev, &dev_attr_inject_data_poison); in edac_create_sysfs_attributes()
1137 device_remove_file(&mci->dev, &dev_attr_inject_data_error); in edac_remove_sysfs_attributes()
1138 device_remove_file(&mci->dev, &dev_attr_inject_data_poison); in edac_remove_sysfs_attributes()
1146 priv->row_shift[0] = (addrmap[5] & ROW_MAX_VAL_MASK) + ROW_B0_BASE; in setup_row_address_map()
1147 priv->row_shift[1] = ((addrmap[5] >> 8) & in setup_row_address_map()
1152 for (index = 2; index < 11; index++) in setup_row_address_map()
1153 priv->row_shift[index] = addrmap_row_b2_10 + in setup_row_address_map()
1157 priv->row_shift[2] = (addrmap[9] & in setup_row_address_map()
1159 priv->row_shift[3] = ((addrmap[9] >> 8) & in setup_row_address_map()
1161 priv->row_shift[4] = ((addrmap[9] >> 16) & in setup_row_address_map()
1163 priv->row_shift[5] = ((addrmap[9] >> 24) & in setup_row_address_map()
1165 priv->row_shift[6] = (addrmap[10] & in setup_row_address_map()
1167 priv->row_shift[7] = ((addrmap[10] >> 8) & in setup_row_address_map()
1169 priv->row_shift[8] = ((addrmap[10] >> 16) & in setup_row_address_map()
1171 priv->row_shift[9] = ((addrmap[10] >> 24) & in setup_row_address_map()
1173 priv->row_shift[10] = (addrmap[11] & in setup_row_address_map()
1177 priv->row_shift[11] = (((addrmap[5] >> 24) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1180 priv->row_shift[12] = ((addrmap[6] & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1183 priv->row_shift[13] = (((addrmap[6] >> 8) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1186 priv->row_shift[14] = (((addrmap[6] >> 16) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1189 priv->row_shift[15] = (((addrmap[6] >> 24) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1192 priv->row_shift[16] = ((addrmap[7] & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1195 priv->row_shift[17] = (((addrmap[7] >> 8) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1205 memtype = readl(priv->baseaddr + CTRL_OFST); in setup_column_address_map()
1208 priv->col_shift[0] = 0; in setup_column_address_map()
1209 priv->col_shift[1] = 1; in setup_column_address_map()
1210 priv->col_shift[2] = (addrmap[2] & COL_MAX_VAL_MASK) + COL_B2_BASE; in setup_column_address_map()
1211 priv->col_shift[3] = ((addrmap[2] >> 8) & in setup_column_address_map()
1213 priv->col_shift[4] = (((addrmap[2] >> 16) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1214 COL_MAX_VAL_MASK) ? 0 : (((addrmap[2] >> 16) & in setup_column_address_map()
1216 priv->col_shift[5] = (((addrmap[2] >> 24) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1217 COL_MAX_VAL_MASK) ? 0 : (((addrmap[2] >> 24) & in setup_column_address_map()
1219 priv->col_shift[6] = ((addrmap[3] & COL_MAX_VAL_MASK) == in setup_column_address_map()
1222 priv->col_shift[7] = (((addrmap[3] >> 8) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1225 priv->col_shift[8] = (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1228 priv->col_shift[9] = (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1233 priv->col_shift[10] = ((addrmap[4] & in setup_column_address_map()
1237 priv->col_shift[11] = (((addrmap[4] >> 8) & in setup_column_address_map()
1242 priv->col_shift[11] = ((addrmap[4] & in setup_column_address_map()
1246 priv->col_shift[13] = (((addrmap[4] >> 8) & in setup_column_address_map()
1253 priv->col_shift[10] = (((addrmap[3] >> 24) & in setup_column_address_map()
1257 priv->col_shift[11] = ((addrmap[4] & in setup_column_address_map()
1262 priv->col_shift[11] = (((addrmap[3] >> 24) & in setup_column_address_map()
1266 priv->col_shift[13] = ((addrmap[4] & in setup_column_address_map()
1273 priv->col_shift[10] = (((addrmap[3] >> 16) & in setup_column_address_map()
1277 priv->col_shift[11] = (((addrmap[3] >> 24) & in setup_column_address_map()
1281 priv->col_shift[13] = ((addrmap[4] & in setup_column_address_map()
1286 priv->col_shift[11] = (((addrmap[3] >> 16) & in setup_column_address_map()
1290 priv->col_shift[13] = (((addrmap[3] >> 24) & in setup_column_address_map()
1298 for (index = 9; index > width; index--) { in setup_column_address_map()
1299 priv->col_shift[index] = priv->col_shift[index - width]; in setup_column_address_map()
1300 priv->col_shift[index - width] = 0; in setup_column_address_map()
1308 priv->bank_shift[0] = (addrmap[1] & BANK_MAX_VAL_MASK) + BANK_B0_BASE; in setup_bank_address_map()
1309 priv->bank_shift[1] = ((addrmap[1] >> 8) & in setup_bank_address_map()
1311 priv->bank_shift[2] = (((addrmap[1] >> 16) & in setup_bank_address_map()
1320 priv->bankgrp_shift[0] = (addrmap[8] & in setup_bg_address_map()
1322 priv->bankgrp_shift[1] = (((addrmap[8] >> 8) & BANKGRP_MAX_VAL_MASK) == in setup_bg_address_map()
1330 priv->rank_shift[0] = ((addrmap[0] & RANK_MAX_VAL_MASK) == in setup_rank_address_map()
1336 * setup_address_map - Set Address Map by querying ADDRMAP registers.
1352 addrmap[index] = readl(priv->baseaddr + addrmap_offset); in setup_address_map()
1368 * mc_probe - Check controller and bind driver.
1379 struct edac_mc_layer layers[2]; in mc_probe()
1387 baseaddr = devm_ioremap_resource(&pdev->dev, res); in mc_probe()
1391 p_data = of_device_get_match_data(&pdev->dev); in mc_probe()
1393 return -ENODEV; in mc_probe()
1395 if (!p_data->get_ecc_state(baseaddr)) { in mc_probe()
1397 return -ENXIO; in mc_probe()
1412 return -ENOMEM; in mc_probe()
1415 priv = mci->pvt_info; in mc_probe()
1416 priv->baseaddr = baseaddr; in mc_probe()
1417 priv->p_data = p_data; in mc_probe()
1418 spin_lock_init(&priv->reglock); in mc_probe()
1422 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in mc_probe()
1436 if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) { in mc_probe()
1445 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) in mc_probe()
1453 if (!(priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)) in mc_probe()
1465 * mc_remove - Unbind driver from controller.
1473 struct synps_edac_priv *priv = mci->pvt_info; in mc_remove()
1475 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) in mc_remove()
1479 if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) in mc_remove()
1483 edac_mc_del_mc(&pdev->dev); in mc_remove()
1491 .name = "synopsys-edac",