Lines Matching +full:tad +full:- +full:page +full:- +full:size
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
24 #include <asm/intel-family.h>
68 0x60, 0x68, 0x70, 0x78, 0x80, /* 0-4 */
69 0x88, 0x90, 0x98, 0xa0, 0xa8, /* 5-9 */
70 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, /* 10-14 */
71 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, /* 15-19 */
72 0x100, 0x108, 0x110, 0x118, /* 20-23 */
105 0x64, 0x6c, 0x74, 0x7c, 0x84, /* 0-4 */
106 0x8c, 0x94, 0x9c, 0xa4, 0xac, /* 5-9 */
107 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, /* 10-14 */
108 0xdc, 0xe4, 0xec, 0xf4, 0xfc, /* 15-19 */
109 0x104, 0x10c, 0x114, 0x11c, /* 20-23 */
205 /* Device 15, functions 2-5 */
251 /* Device 16, functions 2-7 */
291 #define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */
513 * - 1 IMC
514 * - 3 DDR3 channels, 2 DPC per channel
516 * - 1 or 2 IMC
517 * - 4 DDR4 channels, 3 DPC per channel
519 * - 2 IMC
520 * - 4 DDR4 channels, 3 DPC per channel
522 * - 2 IMC
523 * - each IMC interfaces with a SMI 2 channel
524 * - each SMI channel interfaces with a scalable memory buffer
525 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
589 /* Memory controller, TAD tables, error injection - 2-8-0, 2-9-0 (2 of these) */
591 /* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */
593 /* kdrwdbu TAD limits/offsets, MCMTR - 2-10-1, 2-11-1 (2 of these) */
595 /* CHA broadcast registers, dram rules - 1-29-0 (1 of these) */
597 /* SAD target - 1-29-1 (1 of these) */
601 /* Device with TOLM and TOHM, 0-5-0 (1 of these) */
630 * - 1 IMC
631 * - 2 DDR3 channels, 2 DPC per channel
633 * - 1 or 2 IMC
634 * - 4 DDR4 channels, 3 DPC per channel
636 * - 2 IMC
637 * - 4 DDR4 channels, 3 DPC per channel
639 * - 2 IMC
640 * - each IMC interfaces with a SMI 2 channel
641 * - each SMI channel interfaces with a scalable memory buffer
642 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
708 return -EINVAL; in numrank()
721 return -EINVAL; in numrow()
734 return -EINVAL; in numcol()
755 sbridge_dev = list_entry(prev ? prev->list.next in get_sbridge_dev()
759 if ((sbridge_dev->seg == seg) && (sbridge_dev->bus == bus) && in get_sbridge_dev()
760 (dom == SOCK || dom == sbridge_dev->dom)) in get_sbridge_dev()
776 sbridge_dev->pdev = kcalloc(table->n_devs_per_imc, in alloc_sbridge_dev()
777 sizeof(*sbridge_dev->pdev), in alloc_sbridge_dev()
779 if (!sbridge_dev->pdev) { in alloc_sbridge_dev()
784 sbridge_dev->seg = seg; in alloc_sbridge_dev()
785 sbridge_dev->bus = bus; in alloc_sbridge_dev()
786 sbridge_dev->dom = dom; in alloc_sbridge_dev()
787 sbridge_dev->n_devs = table->n_devs_per_imc; in alloc_sbridge_dev()
788 list_add_tail(&sbridge_dev->list, &sbridge_edac_list); in alloc_sbridge_dev()
795 list_del(&sbridge_dev->list); in free_sbridge_dev()
796 kfree(sbridge_dev->pdev); in free_sbridge_dev()
805 pci_read_config_dword(pvt->pci_sad1, TOLM, ®); in sbridge_get_tolm()
813 pci_read_config_dword(pvt->pci_sad1, TOHM, ®); in sbridge_get_tohm()
821 pci_read_config_dword(pvt->pci_br1, TOLM, ®); in ibridge_get_tolm()
830 pci_read_config_dword(pvt->pci_br1, TOHM, ®); in ibridge_get_tohm()
888 if (pvt->pci_ddrio) { in get_memory_type()
889 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr, in get_memory_type()
908 if (!pvt->pci_ddrio) in haswell_get_memory_type()
911 pci_read_config_dword(pvt->pci_ddrio, in haswell_get_memory_type()
917 pci_read_config_dword(pvt->pci_ta, MCMTR, ®); in haswell_get_memory_type()
989 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®); in get_node_id()
997 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); in haswell_get_node_id()
1005 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); in knl_get_node_id()
1022 * home agent bank (7, 8), or one of the per-channel memory
1029 return bank - 7; in ibridge_get_ha()
1031 return (bank - 9) / 4; in ibridge_get_ha()
1047 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®); in haswell_get_tolm()
1056 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®); in haswell_get_tohm()
1058 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®); in haswell_get_tohm()
1068 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, ®); in knl_get_tolm()
1077 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, ®_lo); in knl_get_tohm()
1078 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, ®_hi); in knl_get_tohm()
1086 return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1; in haswell_rir_limit()
1114 /* Low bits of TAD limit, and some metadata. */
1120 /* Low bits of TAD offset. */
1126 /* High 16 bits of TAD limit and offset. */
1132 /* Number of ways a tad entry is interleaved. */
1139 * from the memory controller's TAD table.
1144 * @offset: output tad range offset
1145 * @limit: output address of first byte above tad range
1150 * tad table.
1165 pci_mc = pvt->knl.pci_mc0; in knl_get_tad()
1168 pci_mc = pvt->knl.pci_mc1; in knl_get_tad()
1172 return -EINVAL; in knl_get_tad()
1182 /* Is this TAD entry enabled? */ in knl_get_tad()
1184 return -ENODEV; in knl_get_tad()
1195 return -ENODEV; in knl_get_tad()
1220 * (This is the per-tile mapping of logical interleave targets to
1241 * (This is the per-tile mapping of logical interleave targets to
1269 * Render the EDC_ROUTE register in human-readable form.
1278 s[i*2+1] = '-'; in knl_show_edc_route()
1281 s[KNL_MAX_EDCS*2 - 1] = '\0'; in knl_show_edc_route()
1285 * Render the MC_ROUTE register in human-readable form.
1294 s[i*2+1] = '-'; in knl_show_mc_route()
1297 s[KNL_MAX_CHANNELS*2 - 1] = '\0'; in knl_show_mc_route()
1321 * The DIMMMTR register in KNL doesn't tell us the size of the DIMMs, so we
1323 * and TAD rules.
1325 * SAD rules can have holes in them (e.g. the 3G-4G hole), so we have to
1326 * inspect the TAD rules to figure out how large the SAD regions really are.
1328 * When we know the real size of a SAD region and how many ways it's
1330 * TAD is size/ways.
1338 * case we will underreport the size of the DIMM.)
1355 u64 sad_actual_size[2]; /* sad size accounting for holes, per mc */ in knl_get_dimm_capacity()
1373 pci_read_config_dword(pvt->knl.pci_cha[i], in knl_get_dimm_capacity()
1376 if (i > 0 && edc_route_reg[i] != edc_route_reg[i-1]) { in knl_get_dimm_capacity()
1377 knl_show_edc_route(edc_route_reg[i-1], in knl_get_dimm_capacity()
1379 if (cur_reg_start == i-1) in knl_get_dimm_capacity()
1383 edac_dbg(0, "edc route table for CHA %d-%d: %s\n", in knl_get_dimm_capacity()
1384 cur_reg_start, i-1, edc_route_string); in knl_get_dimm_capacity()
1388 knl_show_edc_route(edc_route_reg[i-1], edc_route_string); in knl_get_dimm_capacity()
1389 if (cur_reg_start == i-1) in knl_get_dimm_capacity()
1393 edac_dbg(0, "edc route table for CHA %d-%d: %s\n", in knl_get_dimm_capacity()
1394 cur_reg_start, i-1, edc_route_string); in knl_get_dimm_capacity()
1399 pci_read_config_dword(pvt->knl.pci_cha[i], in knl_get_dimm_capacity()
1402 if (i > 0 && mc_route_reg[i] != mc_route_reg[i-1]) { in knl_get_dimm_capacity()
1403 knl_show_mc_route(mc_route_reg[i-1], mc_route_string); in knl_get_dimm_capacity()
1404 if (cur_reg_start == i-1) in knl_get_dimm_capacity()
1408 edac_dbg(0, "mc route table for CHA %d-%d: %s\n", in knl_get_dimm_capacity()
1409 cur_reg_start, i-1, mc_route_string); in knl_get_dimm_capacity()
1413 knl_show_mc_route(mc_route_reg[i-1], mc_route_string); in knl_get_dimm_capacity()
1414 if (cur_reg_start == i-1) in knl_get_dimm_capacity()
1418 edac_dbg(0, "mc route table for CHA %d-%d: %s\n", in knl_get_dimm_capacity()
1419 cur_reg_start, i-1, mc_route_string); in knl_get_dimm_capacity()
1422 for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) { in knl_get_dimm_capacity()
1426 pci_read_config_dword(pvt->pci_sad0, in knl_get_dimm_capacity()
1427 pvt->info.dram_rule[sad_rule], &dram_rule); in knl_get_dimm_capacity()
1434 sad_limit = pvt->info.sad_limit(dram_rule)+1; in knl_get_dimm_capacity()
1436 pci_read_config_dword(pvt->pci_sad0, in knl_get_dimm_capacity()
1437 pvt->info.interleave_list[sad_rule], &interleave_reg); in knl_get_dimm_capacity()
1443 first_pkg = sad_pkg(pvt->info.interleave_pkg, in knl_get_dimm_capacity()
1446 pkg = sad_pkg(pvt->info.interleave_pkg, in knl_get_dimm_capacity()
1451 * 0 bit means memory is non-local, in knl_get_dimm_capacity()
1456 return -1; in knl_get_dimm_capacity()
1474 * over TAD tables (SAD regions may contain holes). in knl_get_dimm_capacity()
1475 * Each memory controller might have a different TAD table, so in knl_get_dimm_capacity()
1478 * Livespace is the memory that's mapped in this TAD table, in knl_get_dimm_capacity()
1480 * could be memory that's mapped by the other TAD table but in knl_get_dimm_capacity()
1498 tad_size = (tad_limit+1) - in knl_get_dimm_capacity()
1501 tad_base = (tad_limit+1) - tad_size; in knl_get_dimm_capacity()
1505 …edac_dbg(0, "TAD region overlaps lower SAD boundary -- TAD tables may be configured incorrectly.\n… in knl_get_dimm_capacity()
1508 …edac_dbg(0, "TAD region overlaps upper SAD boundary -- TAD tables may be configured incorrectly.\n… in knl_get_dimm_capacity()
1510 /* TAD region is completely inside SAD region */ in knl_get_dimm_capacity()
1511 edac_dbg(3, "TAD region %d 0x%llx - 0x%llx (%lld bytes) table%d\n", in knl_get_dimm_capacity()
1522 edac_dbg(3, " total TAD DRAM footprint in table%d : 0x%llx (%lld bytes)\n", in knl_get_dimm_capacity()
1571 struct sbridge_pvt *pvt = mci->pvt_info; in get_source_id()
1574 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL || in get_source_id()
1575 pvt->info.type == KNIGHTS_LANDING) in get_source_id()
1576 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®); in get_source_id()
1578 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®); in get_source_id()
1580 if (pvt->info.type == KNIGHTS_LANDING) in get_source_id()
1581 pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg); in get_source_id()
1583 pvt->sbridge_dev->source_id = SOURCE_ID(reg); in get_source_id()
1590 struct sbridge_pvt *pvt = mci->pvt_info; in __populate_dimms()
1591 int channels = pvt->info.type == KNIGHTS_LANDING ? KNL_MAX_CHANNELS in __populate_dimms()
1596 u64 size; in __populate_dimms() local
1598 mtype = pvt->info.get_memory_type(pvt); in __populate_dimms()
1616 if (pvt->info.type == KNIGHTS_LANDING) { in __populate_dimms()
1618 if (!pvt->knl.pci_channel[i]) in __populate_dimms()
1622 if (!pvt->pci_tad[i]) in __populate_dimms()
1624 pci_read_config_dword(pvt->pci_tad[i], 0x8c, &amap); in __populate_dimms()
1629 if (pvt->info.type == KNIGHTS_LANDING) { in __populate_dimms()
1630 pci_read_config_dword(pvt->knl.pci_channel[i], in __populate_dimms()
1633 pci_read_config_dword(pvt->pci_tad[i], in __populate_dimms()
1639 if (!IS_ECC_ENABLED(pvt->info.mcmtr)) { in __populate_dimms()
1641 pvt->sbridge_dev->source_id, in __populate_dimms()
1642 pvt->sbridge_dev->dom, i); in __populate_dimms()
1643 return -ENODEV; in __populate_dimms()
1645 pvt->channel[i].dimms++; in __populate_dimms()
1647 ranks = numrank(pvt->info.type, mtr); in __populate_dimms()
1649 if (pvt->info.type == KNIGHTS_LANDING) { in __populate_dimms()
1659 size = ((u64)rows * cols * banks * ranks) >> (20 - 3); in __populate_dimms()
1660 npages = MiB_TO_PAGES(size); in __populate_dimms()
1663 pvt->sbridge_dev->mc, pvt->sbridge_dev->dom, i, j, in __populate_dimms()
1664 size, npages, in __populate_dimms()
1667 dimm->nr_pages = npages; in __populate_dimms()
1668 dimm->grain = 32; in __populate_dimms()
1669 dimm->dtype = pvt->info.get_width(pvt, mtr); in __populate_dimms()
1670 dimm->mtype = mtype; in __populate_dimms()
1671 dimm->edac_mode = mode; in __populate_dimms()
1672 pvt->channel[i].dimm[j].rowbits = order_base_2(rows); in __populate_dimms()
1673 pvt->channel[i].dimm[j].colbits = order_base_2(cols); in __populate_dimms()
1674 pvt->channel[i].dimm[j].bank_xor_enable = in __populate_dimms()
1675 GET_BITFIELD(pvt->info.mcmtr, 9, 9); in __populate_dimms()
1676 pvt->channel[i].dimm[j].amap_fine = GET_BITFIELD(amap, 0, 0); in __populate_dimms()
1677 snprintf(dimm->label, sizeof(dimm->label), in __populate_dimms()
1679 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom, i, j); in __populate_dimms()
1689 struct sbridge_pvt *pvt = mci->pvt_info; in get_dimm_config()
1694 pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt); in get_dimm_config()
1696 pvt->sbridge_dev->mc, in get_dimm_config()
1697 pvt->sbridge_dev->node_id, in get_dimm_config()
1698 pvt->sbridge_dev->source_id); in get_dimm_config()
1701 * and is always closed page in get_dimm_config()
1703 if (pvt->info.type == KNIGHTS_LANDING) { in get_dimm_config()
1705 pvt->mirror_mode = NON_MIRRORING; in get_dimm_config()
1706 pvt->is_cur_addr_mirrored = false; in get_dimm_config()
1709 return -1; in get_dimm_config()
1710 if (pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr)) { in get_dimm_config()
1712 return -ENODEV; in get_dimm_config()
1715 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { in get_dimm_config()
1716 if (pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®)) { in get_dimm_config()
1718 return -ENODEV; in get_dimm_config()
1720 pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21); in get_dimm_config()
1722 pvt->mirror_mode = ADDR_RANGE_MIRRORING; in get_dimm_config()
1727 if (pci_read_config_dword(pvt->pci_ras, RASENABLES, ®)) { in get_dimm_config()
1729 return -ENODEV; in get_dimm_config()
1732 pvt->mirror_mode = FULL_MIRRORING; in get_dimm_config()
1735 pvt->mirror_mode = NON_MIRRORING; in get_dimm_config()
1740 if (pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr)) { in get_dimm_config()
1742 return -ENODEV; in get_dimm_config()
1744 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { in get_dimm_config()
1747 pvt->is_lockstep = true; in get_dimm_config()
1751 pvt->is_lockstep = false; in get_dimm_config()
1753 if (IS_CLOSE_PG(pvt->info.mcmtr)) { in get_dimm_config()
1754 edac_dbg(0, "address map is on closed page mode\n"); in get_dimm_config()
1755 pvt->is_close_pg = true; in get_dimm_config()
1757 edac_dbg(0, "address map is on open page mode\n"); in get_dimm_config()
1758 pvt->is_close_pg = false; in get_dimm_config()
1767 struct sbridge_pvt *pvt = mci->pvt_info; in get_memory_layout()
1779 pvt->tolm = pvt->info.get_tolm(pvt); in get_memory_layout()
1780 tmp_mb = (1 + pvt->tolm) >> 20; in get_memory_layout()
1784 gb, (mb*1000)/1024, (u64)pvt->tolm); in get_memory_layout()
1787 pvt->tohm = pvt->info.get_tohm(pvt); in get_memory_layout()
1788 tmp_mb = (1 + pvt->tohm) >> 20; in get_memory_layout()
1792 gb, (mb*1000)/1024, (u64)pvt->tohm); in get_memory_layout()
1796 * TAD registers contain the interleave wayness. However, it in get_memory_layout()
1801 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { in get_memory_layout()
1803 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], in get_memory_layout()
1805 limit = pvt->info.sad_limit(reg); in get_memory_layout()
1817 show_dram_attr(pvt->info.dram_attr(reg)), in get_memory_layout()
1820 get_intlv_mode_str(reg, pvt->info.type), in get_memory_layout()
1824 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], in get_memory_layout()
1826 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); in get_memory_layout()
1828 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j); in get_memory_layout()
1837 if (pvt->info.type == KNIGHTS_LANDING) in get_memory_layout()
1841 * Step 3) Get TAD range in get_memory_layout()
1845 pci_read_config_dword(pvt->pci_ha, tad_dram_rule[n_tads], ®); in get_memory_layout()
1852 …edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT:… in get_memory_layout()
1866 * Step 4) Get TAD offsets, per each channel in get_memory_layout()
1869 if (!pvt->channel[i].dimms) in get_memory_layout()
1872 pci_read_config_dword(pvt->pci_tad[i], in get_memory_layout()
1877 edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n", in get_memory_layout()
1889 if (!pvt->channel[i].dimms) in get_memory_layout()
1892 pci_read_config_dword(pvt->pci_tad[i], in get_memory_layout()
1899 tmp_mb = pvt->info.rir_limit(reg) >> 20; in get_memory_layout()
1910 pci_read_config_dword(pvt->pci_tad[i], in get_memory_layout()
1913 tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6; in get_memory_layout()
1920 (u32)RIR_RNK_TGT(pvt->info.type, reg), in get_memory_layout()
1932 if (sbridge_dev->node_id == node_id && sbridge_dev->dom == ha) in get_mci_for_node_id()
1933 return sbridge_dev->mci; in get_mci_for_node_id()
1987 pvt = mci->pvt_info; in sb_decode_ddr4()
1988 amap_fine = pvt->channel[ch].dimm[dimmno].amap_fine; in sb_decode_ddr4()
1990 rowbits = pvt->channel[ch].dimm[dimmno].rowbits; in sb_decode_ddr4()
1991 colbits = pvt->channel[ch].dimm[dimmno].colbits; in sb_decode_ddr4()
1992 bank_xor_enable = pvt->channel[ch].dimm[dimmno].bank_xor_enable; in sb_decode_ddr4()
1994 if (pvt->is_lockstep) { in sb_decode_ddr4()
2000 if (pvt->is_close_pg) { in sb_decode_ddr4()
2016 row &= (1u << rowbits) - 1; in sb_decode_ddr4()
2039 struct sbridge_pvt *pvt = mci->pvt_info; in get_memory_error_data()
2061 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) { in get_memory_error_data()
2063 return -EINVAL; in get_memory_error_data()
2065 if (addr >= (u64)pvt->tohm) { in get_memory_error_data()
2067 return -EINVAL; in get_memory_error_data()
2073 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { in get_memory_error_data()
2074 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], in get_memory_error_data()
2080 limit = pvt->info.sad_limit(reg); in get_memory_error_data()
2083 return -EINVAL; in get_memory_error_data()
2089 if (n_sads == pvt->info.max_sad) { in get_memory_error_data()
2091 return -EINVAL; in get_memory_error_data()
2094 *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule)); in get_memory_error_data()
2095 interleave_mode = pvt->info.interleave_mode(dram_rule); in get_memory_error_data()
2097 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], in get_memory_error_data()
2100 if (pvt->info.type == SANDY_BRIDGE) { in get_memory_error_data()
2101 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); in get_memory_error_data()
2103 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way); in get_memory_error_data()
2111 pvt->sbridge_dev->mc, in get_memory_error_data()
2135 return -EINVAL; in get_memory_error_data()
2140 } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { in get_memory_error_data()
2157 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); in get_memory_error_data()
2163 pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®); in get_memory_error_data()
2172 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); in get_memory_error_data()
2189 return -EINVAL; in get_memory_error_data()
2192 pvt = mci->pvt_info; in get_memory_error_data()
2198 pci_ha = pvt->pci_ha; in get_memory_error_data()
2204 return -EINVAL; in get_memory_error_data()
2212 return -EINVAL; in get_memory_error_data()
2222 if (pvt->is_chan_hash) in get_memory_error_data()
2244 sprintf(msg, "Can't discover the TAD target"); in get_memory_error_data()
2245 return -EINVAL; in get_memory_error_data()
2249 pci_read_config_dword(pvt->pci_tad[base_ch], tad_ch_nilv_offset[n_tads], &tad_offset); in get_memory_error_data()
2251 if (pvt->mirror_mode == FULL_MIRRORING || in get_memory_error_data()
2252 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && n_tads == 0)) { in get_memory_error_data()
2261 return -EINVAL; in get_memory_error_data()
2264 pvt->is_cur_addr_mirrored = true; in get_memory_error_data()
2267 pvt->is_cur_addr_mirrored = false; in get_memory_error_data()
2270 if (pvt->is_lockstep) in get_memory_error_data()
2275 …edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (off… in get_memory_error_data()
2287 /* Remove the TAD offset */ in get_memory_error_data()
2290 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!", in get_memory_error_data()
2292 return -EINVAL; in get_memory_error_data()
2295 ch_addr = addr - offset; in get_memory_error_data()
2299 ch_addr |= addr & ((1 << (6 + shiftup)) - 1); in get_memory_error_data()
2305 pci_read_config_dword(pvt->pci_tad[base_ch], rir_way_limit[n_rir], ®); in get_memory_error_data()
2310 limit = pvt->info.rir_limit(reg); in get_memory_error_data()
2323 return -EINVAL; in get_memory_error_data()
2327 if (pvt->is_close_pg) in get_memory_error_data()
2333 pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], ®); in get_memory_error_data()
2334 *rank = RIR_RNK_TGT(pvt->info.type, reg); in get_memory_error_data()
2336 if (pvt->info.type == BROADWELL) { in get_memory_error_data()
2337 if (pvt->is_close_pg) in get_memory_error_data()
2345 rank_addr |= ch_addr & GENMASK_ULL(shiftup - 1, 0); in get_memory_error_data()
2346 rank_addr -= RIR_OFFSET(pvt->info.type, reg); in get_memory_error_data()
2348 mtype = pvt->info.get_memory_type(pvt); in get_memory_error_data()
2373 u32 reg, channel = GET_BITFIELD(m->status, 0, 3); in get_memory_error_data_from_mce()
2381 return -EINVAL; in get_memory_error_data_from_mce()
2384 pvt = mci->pvt_info; in get_memory_error_data_from_mce()
2385 if (!pvt->info.get_ha) { in get_memory_error_data_from_mce()
2387 return -EINVAL; in get_memory_error_data_from_mce()
2389 *ha = pvt->info.get_ha(m->bank); in get_memory_error_data_from_mce()
2391 sprintf(msg, "Impossible bank %d", m->bank); in get_memory_error_data_from_mce()
2392 return -EINVAL; in get_memory_error_data_from_mce()
2395 *socket = m->socketid; in get_memory_error_data_from_mce()
2399 return -EINVAL; in get_memory_error_data_from_mce()
2402 pvt = new_mci->pvt_info; in get_memory_error_data_from_mce()
2403 pci_ha = pvt->pci_ha; in get_memory_error_data_from_mce()
2405 tad0 = m->addr <= TAD_LIMIT(reg); in get_memory_error_data_from_mce()
2408 if (pvt->mirror_mode == FULL_MIRRORING || in get_memory_error_data_from_mce()
2409 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && tad0)) { in get_memory_error_data_from_mce()
2411 pvt->is_cur_addr_mirrored = true; in get_memory_error_data_from_mce()
2413 pvt->is_cur_addr_mirrored = false; in get_memory_error_data_from_mce()
2416 if (pvt->is_lockstep) in get_memory_error_data_from_mce()
2435 for (i = 0; i < sbridge_dev->n_devs; i++) { in sbridge_put_devices()
2436 struct pci_dev *pdev = sbridge_dev->pdev[i]; in sbridge_put_devices()
2440 pdev->bus->number, in sbridge_put_devices()
2441 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); in sbridge_put_devices()
2463 const struct pci_id_descr *dev_descr = &table->descr[devno]; in sbridge_get_onedevice()
2471 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); in sbridge_get_onedevice()
2474 dev_descr->dev_id, *prev); in sbridge_get_onedevice()
2482 if (dev_descr->optional) in sbridge_get_onedevice()
2487 return -ENODEV; in sbridge_get_onedevice()
2491 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); in sbridge_get_onedevice()
2494 return -ENODEV; in sbridge_get_onedevice()
2496 seg = pci_domain_nr(pdev->bus); in sbridge_get_onedevice()
2497 bus = pdev->bus->number; in sbridge_get_onedevice()
2500 sbridge_dev = get_sbridge_dev(seg, bus, dev_descr->dom, in sbridge_get_onedevice()
2504 if (dev_descr->dom == IMC1 && devno != 1) { in sbridge_get_onedevice()
2506 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); in sbridge_get_onedevice()
2511 if (dev_descr->dom == SOCK) in sbridge_get_onedevice()
2514 sbridge_dev = alloc_sbridge_dev(seg, bus, dev_descr->dom, table); in sbridge_get_onedevice()
2517 return -ENOMEM; in sbridge_get_onedevice()
2522 if (sbridge_dev->pdev[sbridge_dev->i_devs]) { in sbridge_get_onedevice()
2525 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); in sbridge_get_onedevice()
2527 return -ENODEV; in sbridge_get_onedevice()
2530 sbridge_dev->pdev[sbridge_dev->i_devs++] = pdev; in sbridge_get_onedevice()
2536 if (dev_descr->dom == SOCK && i < table->n_imcs_per_sock) in sbridge_get_onedevice()
2544 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); in sbridge_get_onedevice()
2545 return -ENODEV; in sbridge_get_onedevice()
2549 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); in sbridge_get_onedevice()
2564 * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's
2580 if (table->type == KNIGHTS_LANDING) in sbridge_get_all_devices()
2582 while (table && table->descr) { in sbridge_get_all_devices()
2583 for (i = 0; i < table->n_devs_per_sock; i++) { in sbridge_get_all_devices()
2585 table->descr[i].dev_id != in sbridge_get_all_devices()
2586 table->descr[i-1].dev_id) { in sbridge_get_all_devices()
2594 i = table->n_devs_per_sock; in sbridge_get_all_devices()
2598 return -ENODEV; in sbridge_get_all_devices()
2613 #define TAD_DEV_TO_CHAN(dev) (((dev) & 0xf) - 0xa)
2618 struct sbridge_pvt *pvt = mci->pvt_info; in sbridge_mci_bind_devs()
2623 for (i = 0; i < sbridge_dev->n_devs; i++) { in sbridge_mci_bind_devs()
2624 pdev = sbridge_dev->pdev[i]; in sbridge_mci_bind_devs()
2628 switch (pdev->device) { in sbridge_mci_bind_devs()
2630 pvt->pci_sad0 = pdev; in sbridge_mci_bind_devs()
2633 pvt->pci_sad1 = pdev; in sbridge_mci_bind_devs()
2636 pvt->pci_br0 = pdev; in sbridge_mci_bind_devs()
2639 pvt->pci_ha = pdev; in sbridge_mci_bind_devs()
2642 pvt->pci_ta = pdev; in sbridge_mci_bind_devs()
2645 pvt->pci_ras = pdev; in sbridge_mci_bind_devs()
2652 int id = TAD_DEV_TO_CHAN(pdev->device); in sbridge_mci_bind_devs()
2653 pvt->pci_tad[id] = pdev; in sbridge_mci_bind_devs()
2658 pvt->pci_ddrio = pdev; in sbridge_mci_bind_devs()
2665 pdev->vendor, pdev->device, in sbridge_mci_bind_devs()
2666 sbridge_dev->bus, in sbridge_mci_bind_devs()
2671 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha || in sbridge_mci_bind_devs()
2672 !pvt->pci_ras || !pvt->pci_ta) in sbridge_mci_bind_devs()
2681 return -ENODEV; in sbridge_mci_bind_devs()
2685 PCI_VENDOR_ID_INTEL, pdev->device); in sbridge_mci_bind_devs()
2686 return -EINVAL; in sbridge_mci_bind_devs()
2692 struct sbridge_pvt *pvt = mci->pvt_info; in ibridge_mci_bind_devs()
2697 for (i = 0; i < sbridge_dev->n_devs; i++) { in ibridge_mci_bind_devs()
2698 pdev = sbridge_dev->pdev[i]; in ibridge_mci_bind_devs()
2702 switch (pdev->device) { in ibridge_mci_bind_devs()
2705 pvt->pci_ha = pdev; in ibridge_mci_bind_devs()
2709 pvt->pci_ta = pdev; in ibridge_mci_bind_devs()
2713 pvt->pci_ras = pdev; in ibridge_mci_bind_devs()
2724 int id = TAD_DEV_TO_CHAN(pdev->device); in ibridge_mci_bind_devs()
2725 pvt->pci_tad[id] = pdev; in ibridge_mci_bind_devs()
2730 pvt->pci_ddrio = pdev; in ibridge_mci_bind_devs()
2733 pvt->pci_ddrio = pdev; in ibridge_mci_bind_devs()
2736 pvt->pci_sad0 = pdev; in ibridge_mci_bind_devs()
2739 pvt->pci_br0 = pdev; in ibridge_mci_bind_devs()
2742 pvt->pci_br1 = pdev; in ibridge_mci_bind_devs()
2749 sbridge_dev->bus, in ibridge_mci_bind_devs()
2750 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), in ibridge_mci_bind_devs()
2755 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_br0 || in ibridge_mci_bind_devs()
2756 !pvt->pci_br1 || !pvt->pci_ras || !pvt->pci_ta) in ibridge_mci_bind_devs()
2759 if (saw_chan_mask != 0x0f && /* -EN/-EX */ in ibridge_mci_bind_devs()
2760 saw_chan_mask != 0x03) /* -EP */ in ibridge_mci_bind_devs()
2766 return -ENODEV; in ibridge_mci_bind_devs()
2771 pdev->device); in ibridge_mci_bind_devs()
2772 return -EINVAL; in ibridge_mci_bind_devs()
2778 struct sbridge_pvt *pvt = mci->pvt_info; in haswell_mci_bind_devs()
2784 if (pvt->info.pci_vtd == NULL) in haswell_mci_bind_devs()
2786 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, in haswell_mci_bind_devs()
2790 for (i = 0; i < sbridge_dev->n_devs; i++) { in haswell_mci_bind_devs()
2791 pdev = sbridge_dev->pdev[i]; in haswell_mci_bind_devs()
2795 switch (pdev->device) { in haswell_mci_bind_devs()
2797 pvt->pci_sad0 = pdev; in haswell_mci_bind_devs()
2800 pvt->pci_sad1 = pdev; in haswell_mci_bind_devs()
2804 pvt->pci_ha = pdev; in haswell_mci_bind_devs()
2808 pvt->pci_ta = pdev; in haswell_mci_bind_devs()
2812 pvt->pci_ras = pdev; in haswell_mci_bind_devs()
2823 int id = TAD_DEV_TO_CHAN(pdev->device); in haswell_mci_bind_devs()
2824 pvt->pci_tad[id] = pdev; in haswell_mci_bind_devs()
2832 if (!pvt->pci_ddrio) in haswell_mci_bind_devs()
2833 pvt->pci_ddrio = pdev; in haswell_mci_bind_devs()
2840 sbridge_dev->bus, in haswell_mci_bind_devs()
2841 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), in haswell_mci_bind_devs()
2846 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 || in haswell_mci_bind_devs()
2847 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) in haswell_mci_bind_devs()
2850 if (saw_chan_mask != 0x0f && /* -EN/-EX */ in haswell_mci_bind_devs()
2851 saw_chan_mask != 0x03) /* -EP */ in haswell_mci_bind_devs()
2857 return -ENODEV; in haswell_mci_bind_devs()
2863 struct sbridge_pvt *pvt = mci->pvt_info; in broadwell_mci_bind_devs()
2869 if (pvt->info.pci_vtd == NULL) in broadwell_mci_bind_devs()
2871 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, in broadwell_mci_bind_devs()
2875 for (i = 0; i < sbridge_dev->n_devs; i++) { in broadwell_mci_bind_devs()
2876 pdev = sbridge_dev->pdev[i]; in broadwell_mci_bind_devs()
2880 switch (pdev->device) { in broadwell_mci_bind_devs()
2882 pvt->pci_sad0 = pdev; in broadwell_mci_bind_devs()
2885 pvt->pci_sad1 = pdev; in broadwell_mci_bind_devs()
2889 pvt->pci_ha = pdev; in broadwell_mci_bind_devs()
2893 pvt->pci_ta = pdev; in broadwell_mci_bind_devs()
2897 pvt->pci_ras = pdev; in broadwell_mci_bind_devs()
2908 int id = TAD_DEV_TO_CHAN(pdev->device); in broadwell_mci_bind_devs()
2909 pvt->pci_tad[id] = pdev; in broadwell_mci_bind_devs()
2914 pvt->pci_ddrio = pdev; in broadwell_mci_bind_devs()
2921 sbridge_dev->bus, in broadwell_mci_bind_devs()
2922 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), in broadwell_mci_bind_devs()
2927 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 || in broadwell_mci_bind_devs()
2928 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) in broadwell_mci_bind_devs()
2931 if (saw_chan_mask != 0x0f && /* -EN/-EX */ in broadwell_mci_bind_devs()
2932 saw_chan_mask != 0x03) /* -EP */ in broadwell_mci_bind_devs()
2938 return -ENODEV; in broadwell_mci_bind_devs()
2944 struct sbridge_pvt *pvt = mci->pvt_info; in knl_mci_bind_devs()
2951 for (i = 0; i < sbridge_dev->n_devs; i++) { in knl_mci_bind_devs()
2952 pdev = sbridge_dev->pdev[i]; in knl_mci_bind_devs()
2957 dev = (pdev->devfn >> 3) & 0x1f; in knl_mci_bind_devs()
2958 func = pdev->devfn & 0x7; in knl_mci_bind_devs()
2960 switch (pdev->device) { in knl_mci_bind_devs()
2963 pvt->knl.pci_mc0 = pdev; in knl_mci_bind_devs()
2965 pvt->knl.pci_mc1 = pdev; in knl_mci_bind_devs()
2975 pvt->pci_sad0 = pdev; in knl_mci_bind_devs()
2979 pvt->pci_sad1 = pdev; in knl_mci_bind_devs()
2986 devidx = ((dev-14)*8)+func; in knl_mci_bind_devs()
2995 WARN_ON(pvt->knl.pci_cha[devidx] != NULL); in knl_mci_bind_devs()
2997 pvt->knl.pci_cha[devidx] = pdev; in knl_mci_bind_devs()
3001 devidx = -1; in knl_mci_bind_devs()
3004 * MC0 channels 0-2 are device 9 function 2-4, in knl_mci_bind_devs()
3005 * MC1 channels 3-5 are device 8 function 2-4. in knl_mci_bind_devs()
3009 devidx = func-2; in knl_mci_bind_devs()
3011 devidx = 3 + (func-2); in knl_mci_bind_devs()
3020 WARN_ON(pvt->knl.pci_channel[devidx] != NULL); in knl_mci_bind_devs()
3021 pvt->knl.pci_channel[devidx] = pdev; in knl_mci_bind_devs()
3025 pvt->knl.pci_mc_info = pdev; in knl_mci_bind_devs()
3029 pvt->pci_ta = pdev; in knl_mci_bind_devs()
3034 pdev->device); in knl_mci_bind_devs()
3039 if (!pvt->knl.pci_mc0 || !pvt->knl.pci_mc1 || in knl_mci_bind_devs()
3040 !pvt->pci_sad0 || !pvt->pci_sad1 || in knl_mci_bind_devs()
3041 !pvt->pci_ta) { in knl_mci_bind_devs()
3046 if (!pvt->knl.pci_channel[i]) { in knl_mci_bind_devs()
3053 if (!pvt->knl.pci_cha[i]) { in knl_mci_bind_devs()
3063 return -ENODEV; in knl_mci_bind_devs()
3080 struct sbridge_pvt *pvt = mci->pvt_info; in sbridge_mce_output_error()
3083 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0); in sbridge_mce_output_error()
3084 bool overflow = GET_BITFIELD(m->status, 62, 62); in sbridge_mce_output_error()
3085 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61); in sbridge_mce_output_error()
3087 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); in sbridge_mce_output_error()
3088 u32 mscod = GET_BITFIELD(m->status, 16, 31); in sbridge_mce_output_error()
3089 u32 errcode = GET_BITFIELD(m->status, 0, 15); in sbridge_mce_output_error()
3090 u32 channel = GET_BITFIELD(m->status, 0, 3); in sbridge_mce_output_error()
3091 u32 optypenum = GET_BITFIELD(m->status, 4, 6); in sbridge_mce_output_error()
3093 * Bits 5-0 of MCi_MISC give the least significant bit that is valid. in sbridge_mce_output_error()
3094 * A value 6 is for cache line aligned address, a value 12 is for page in sbridge_mce_output_error()
3097 u32 lsb = GET_BITFIELD(m->misc, 0, 5); in sbridge_mce_output_error()
3103 if (pvt->info.type != SANDY_BRIDGE) in sbridge_mce_output_error()
3106 recoverable = GET_BITFIELD(m->status, 56, 56); in sbridge_mce_output_error()
3120 * According with Table 15-9 of the Intel Architecture spec vol 3A, in sbridge_mce_output_error()
3151 if (pvt->info.type == KNIGHTS_LANDING) { in sbridge_mce_output_error()
3158 m->bank); in sbridge_mce_output_error()
3163 * Reported channel is in range 0-2, so we can't map it in sbridge_mce_output_error()
3168 channel = knl_channel_remap(m->bank == 16, channel); in sbridge_mce_output_error()
3178 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, in sbridge_mce_output_error()
3179 channel, 0, -1, in sbridge_mce_output_error()
3184 rc = get_memory_error_data(mci, m->addr, &socket, &ha, in sbridge_mce_output_error()
3200 pvt = mci->pvt_info; in sbridge_mce_output_error()
3205 dimm = -1; in sbridge_mce_output_error()
3219 if (!pvt->is_lockstep && !pvt->is_cur_addr_mirrored && !pvt->is_close_pg) in sbridge_mce_output_error()
3236 channel = -1; in sbridge_mce_output_error()
3240 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, in sbridge_mce_output_error()
3241 channel, dimm, -1, in sbridge_mce_output_error()
3246 -1, -1, -1, in sbridge_mce_output_error()
3262 if (mce->kflags & MCE_HANDLED_CEC) in sbridge_mce_check_error()
3268 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0. in sbridge_mce_check_error()
3271 if ((mce->status & 0xefff) >> 7 != 1) in sbridge_mce_check_error()
3275 if (!GET_BITFIELD(mce->status, 58, 58)) in sbridge_mce_check_error()
3279 if (!GET_BITFIELD(mce->status, 59, 59)) in sbridge_mce_check_error()
3283 if (GET_BITFIELD(mce->misc, 6, 8) != 2) in sbridge_mce_check_error()
3286 mci = get_mci_for_node_id(mce->socketid, IMC0); in sbridge_mce_check_error()
3290 if (mce->mcgstatus & MCG_STATUS_MCIP) in sbridge_mce_check_error()
3298 "Bank %d: %016Lx\n", mce->extcpu, type, in sbridge_mce_check_error()
3299 mce->mcgstatus, mce->bank, mce->status); in sbridge_mce_check_error()
3300 sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc); in sbridge_mce_check_error()
3301 sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr); in sbridge_mce_check_error()
3302 sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc); in sbridge_mce_check_error()
3305 "%u APIC %x\n", mce->cpuvendor, mce->cpuid, in sbridge_mce_check_error()
3306 mce->time, mce->socketid, mce->apicid); in sbridge_mce_check_error()
3311 mce->kflags |= MCE_HANDLED_EDAC; in sbridge_mce_check_error()
3326 struct mem_ctl_info *mci = sbridge_dev->mci; in sbridge_unregister_mci()
3328 if (unlikely(!mci || !mci->pvt_info)) { in sbridge_unregister_mci()
3329 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev); in sbridge_unregister_mci()
3336 mci, &sbridge_dev->pdev[0]->dev); in sbridge_unregister_mci()
3339 edac_mc_del_mc(mci->pdev); in sbridge_unregister_mci()
3341 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); in sbridge_unregister_mci()
3342 kfree(mci->ctl_name); in sbridge_unregister_mci()
3344 sbridge_dev->mci = NULL; in sbridge_unregister_mci()
3352 struct pci_dev *pdev = sbridge_dev->pdev[0]; in sbridge_register_mci()
3357 layers[0].size = type == KNIGHTS_LANDING ? in sbridge_register_mci()
3361 layers[1].size = type == KNIGHTS_LANDING ? 1 : MAX_DIMMS; in sbridge_register_mci()
3363 mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers, in sbridge_register_mci()
3367 return -ENOMEM; in sbridge_register_mci()
3370 mci, &pdev->dev); in sbridge_register_mci()
3372 pvt = mci->pvt_info; in sbridge_register_mci()
3376 pvt->sbridge_dev = sbridge_dev; in sbridge_register_mci()
3377 sbridge_dev->mci = mci; in sbridge_register_mci()
3379 mci->mtype_cap = type == KNIGHTS_LANDING ? in sbridge_register_mci()
3381 mci->edac_ctl_cap = EDAC_FLAG_NONE; in sbridge_register_mci()
3382 mci->edac_cap = EDAC_FLAG_NONE; in sbridge_register_mci()
3383 mci->mod_name = EDAC_MOD_STR; in sbridge_register_mci()
3384 mci->dev_name = pci_name(pdev); in sbridge_register_mci()
3385 mci->ctl_page_to_phys = NULL; in sbridge_register_mci()
3387 pvt->info.type = type; in sbridge_register_mci()
3390 pvt->info.rankcfgr = IB_RANK_CFG_A; in sbridge_register_mci()
3391 pvt->info.get_tolm = ibridge_get_tolm; in sbridge_register_mci()
3392 pvt->info.get_tohm = ibridge_get_tohm; in sbridge_register_mci()
3393 pvt->info.dram_rule = ibridge_dram_rule; in sbridge_register_mci()
3394 pvt->info.get_memory_type = get_memory_type; in sbridge_register_mci()
3395 pvt->info.get_node_id = get_node_id; in sbridge_register_mci()
3396 pvt->info.get_ha = ibridge_get_ha; in sbridge_register_mci()
3397 pvt->info.rir_limit = rir_limit; in sbridge_register_mci()
3398 pvt->info.sad_limit = sad_limit; in sbridge_register_mci()
3399 pvt->info.interleave_mode = interleave_mode; in sbridge_register_mci()
3400 pvt->info.dram_attr = dram_attr; in sbridge_register_mci()
3401 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); in sbridge_register_mci()
3402 pvt->info.interleave_list = ibridge_interleave_list; in sbridge_register_mci()
3403 pvt->info.interleave_pkg = ibridge_interleave_pkg; in sbridge_register_mci()
3404 pvt->info.get_width = ibridge_get_width; in sbridge_register_mci()
3411 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge SrcID#%d_Ha#%d", in sbridge_register_mci()
3412 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3415 pvt->info.rankcfgr = SB_RANK_CFG_A; in sbridge_register_mci()
3416 pvt->info.get_tolm = sbridge_get_tolm; in sbridge_register_mci()
3417 pvt->info.get_tohm = sbridge_get_tohm; in sbridge_register_mci()
3418 pvt->info.dram_rule = sbridge_dram_rule; in sbridge_register_mci()
3419 pvt->info.get_memory_type = get_memory_type; in sbridge_register_mci()
3420 pvt->info.get_node_id = get_node_id; in sbridge_register_mci()
3421 pvt->info.get_ha = sbridge_get_ha; in sbridge_register_mci()
3422 pvt->info.rir_limit = rir_limit; in sbridge_register_mci()
3423 pvt->info.sad_limit = sad_limit; in sbridge_register_mci()
3424 pvt->info.interleave_mode = interleave_mode; in sbridge_register_mci()
3425 pvt->info.dram_attr = dram_attr; in sbridge_register_mci()
3426 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule); in sbridge_register_mci()
3427 pvt->info.interleave_list = sbridge_interleave_list; in sbridge_register_mci()
3428 pvt->info.interleave_pkg = sbridge_interleave_pkg; in sbridge_register_mci()
3429 pvt->info.get_width = sbridge_get_width; in sbridge_register_mci()
3436 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge SrcID#%d_Ha#%d", in sbridge_register_mci()
3437 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3441 pvt->info.get_tolm = haswell_get_tolm; in sbridge_register_mci()
3442 pvt->info.get_tohm = haswell_get_tohm; in sbridge_register_mci()
3443 pvt->info.dram_rule = ibridge_dram_rule; in sbridge_register_mci()
3444 pvt->info.get_memory_type = haswell_get_memory_type; in sbridge_register_mci()
3445 pvt->info.get_node_id = haswell_get_node_id; in sbridge_register_mci()
3446 pvt->info.get_ha = ibridge_get_ha; in sbridge_register_mci()
3447 pvt->info.rir_limit = haswell_rir_limit; in sbridge_register_mci()
3448 pvt->info.sad_limit = sad_limit; in sbridge_register_mci()
3449 pvt->info.interleave_mode = interleave_mode; in sbridge_register_mci()
3450 pvt->info.dram_attr = dram_attr; in sbridge_register_mci()
3451 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); in sbridge_register_mci()
3452 pvt->info.interleave_list = ibridge_interleave_list; in sbridge_register_mci()
3453 pvt->info.interleave_pkg = ibridge_interleave_pkg; in sbridge_register_mci()
3454 pvt->info.get_width = ibridge_get_width; in sbridge_register_mci()
3461 mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell SrcID#%d_Ha#%d", in sbridge_register_mci()
3462 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3466 pvt->info.get_tolm = haswell_get_tolm; in sbridge_register_mci()
3467 pvt->info.get_tohm = haswell_get_tohm; in sbridge_register_mci()
3468 pvt->info.dram_rule = ibridge_dram_rule; in sbridge_register_mci()
3469 pvt->info.get_memory_type = haswell_get_memory_type; in sbridge_register_mci()
3470 pvt->info.get_node_id = haswell_get_node_id; in sbridge_register_mci()
3471 pvt->info.get_ha = ibridge_get_ha; in sbridge_register_mci()
3472 pvt->info.rir_limit = haswell_rir_limit; in sbridge_register_mci()
3473 pvt->info.sad_limit = sad_limit; in sbridge_register_mci()
3474 pvt->info.interleave_mode = interleave_mode; in sbridge_register_mci()
3475 pvt->info.dram_attr = dram_attr; in sbridge_register_mci()
3476 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); in sbridge_register_mci()
3477 pvt->info.interleave_list = ibridge_interleave_list; in sbridge_register_mci()
3478 pvt->info.interleave_pkg = ibridge_interleave_pkg; in sbridge_register_mci()
3479 pvt->info.get_width = broadwell_get_width; in sbridge_register_mci()
3486 mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell SrcID#%d_Ha#%d", in sbridge_register_mci()
3487 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3490 /* pvt->info.rankcfgr == ??? */ in sbridge_register_mci()
3491 pvt->info.get_tolm = knl_get_tolm; in sbridge_register_mci()
3492 pvt->info.get_tohm = knl_get_tohm; in sbridge_register_mci()
3493 pvt->info.dram_rule = knl_dram_rule; in sbridge_register_mci()
3494 pvt->info.get_memory_type = knl_get_memory_type; in sbridge_register_mci()
3495 pvt->info.get_node_id = knl_get_node_id; in sbridge_register_mci()
3496 pvt->info.get_ha = knl_get_ha; in sbridge_register_mci()
3497 pvt->info.rir_limit = NULL; in sbridge_register_mci()
3498 pvt->info.sad_limit = knl_sad_limit; in sbridge_register_mci()
3499 pvt->info.interleave_mode = knl_interleave_mode; in sbridge_register_mci()
3500 pvt->info.dram_attr = dram_attr_knl; in sbridge_register_mci()
3501 pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule); in sbridge_register_mci()
3502 pvt->info.interleave_list = knl_interleave_list; in sbridge_register_mci()
3503 pvt->info.interleave_pkg = ibridge_interleave_pkg; in sbridge_register_mci()
3504 pvt->info.get_width = knl_get_width; in sbridge_register_mci()
3510 mci->ctl_name = kasprintf(GFP_KERNEL, "Knights Landing SrcID#%d_Ha#%d", in sbridge_register_mci()
3511 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3515 if (!mci->ctl_name) { in sbridge_register_mci()
3516 rc = -ENOMEM; in sbridge_register_mci()
3529 mci->pdev = &pdev->dev; in sbridge_register_mci()
3534 rc = -EINVAL; in sbridge_register_mci()
3541 kfree(mci->ctl_name); in sbridge_register_mci()
3544 sbridge_dev->mci = NULL; in sbridge_register_mci()
3573 struct pci_id_table *ptable = (struct pci_id_table *)id->driver_data; in sbridge_probe()
3589 sbridge_dev->mc = mc++; in sbridge_probe()
3590 rc = sbridge_register_mci(sbridge_dev, ptable->type); in sbridge_probe()
3638 return -EBUSY; in sbridge_init()
3642 return -EBUSY; in sbridge_init()
3645 return -ENODEV; in sbridge_init()
3649 return -ENODEV; in sbridge_init()
3687 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "