Lines Matching +full:lo +full:- +full:sideband
1 // SPDX-License-Identifier: GPL-2.0-only
34 #include <asm/intel-family.h>
111 #define SELECTOR_DISABLED (-1)
125 #define GET_BITFIELD(v, lo, hi) (((v) & GENMASK_ULL(hi, lo)) >> (lo)) argument
130 * side-band mailbox style interface in a hidden PCI device
168 ret = -EAGAIN; in _apl_rd_reg()
179 if (retries-- == 0) { in _apl_rd_reg()
180 ret = -EBUSY; in _apl_rd_reg()
216 struct b_cr_mchbar_lo_pci lo; in get_mem_ctrl_hub_base_addr() local
222 pci_read_config_dword(pdev, 0x48, (u32 *)&lo); in get_mem_ctrl_hub_base_addr()
229 if (!lo.enable) { in get_mem_ctrl_hub_base_addr()
234 return U64_LSHIFT(hi.base, 32) | U64_LSHIFT(lo.base, 15); in get_mem_ctrl_hub_base_addr()
249 return -ENODEV; in dnv_rd_reg()
260 return -ENODEV; in dnv_rd_reg()
261 r.end = r.start + DNV_MCHBAR_SIZE - 1; in dnv_rd_reg()
263 /* MMIO via sideband register base address */ in dnv_rd_reg()
269 r.end = r.start + DNV_SB_PORT_SIZE - 1; in dnv_rd_reg()
274 return -ENODEV; in dnv_rd_reg()
291 ops->rd_reg(port, \
298 ops->rd_reg(regname ## _port, \
312 static int slice_selector = -1;
313 static int chan_selector = -1;
319 rp->enabled = 1; in mk_region()
320 rp->base = base; in mk_region()
321 rp->limit = limit; in mk_region()
339 rp->base = base; in mk_region_mask()
340 rp->limit = (base | ~mask) & GENMASK_ULL(PND_MAX_PHYS_BIT, 0); in mk_region_mask()
341 rp->enabled = 1; in mk_region_mask()
342 edac_dbg(2, "Region:%s [%llx, %llx]\n", name, base, rp->limit); in mk_region_mask()
347 if (!rp->enabled) in in_region()
350 return rp->base <= addr && addr <= rp->limit; in in_region()
357 if (!p->slice_0_mem_disabled) in gen_sym_mask()
358 mask |= p->sym_slice0_channel_enabled; in gen_sym_mask()
360 if (!p->slice_1_disabled) in gen_sym_mask()
361 mask |= p->sym_slice1_channel_enabled << 2; in gen_sym_mask()
363 if (p->ch_1_disabled || p->enable_pmi_dual_data_mode) in gen_sym_mask()
377 if (as2way->asym_2way_interleave_enable) in gen_asym_mask()
378 mask = intlv[as2way->asym_2way_intlv_mode]; in gen_asym_mask()
379 if (as0->slice0_asym_enable) in gen_asym_mask()
380 mask |= (1 << as0->slice0_asym_channel_select); in gen_asym_mask()
381 if (as1->slice1_asym_enable) in gen_asym_mask()
382 mask |= (4 << as1->slice1_asym_channel_select); in gen_asym_mask()
383 if (p->slice_0_mem_disabled) in gen_asym_mask()
385 if (p->slice_1_disabled) in gen_asym_mask()
387 if (p->ch_1_disabled || p->enable_pmi_dual_data_mode) in gen_asym_mask()
429 U64_LSHIFT(a->slice0_asym_base, APL_ASYMSHIFT), in apl_mk_region()
430 U64_LSHIFT(a->slice0_asym_limit, APL_ASYMSHIFT) + in apl_mk_region()
431 GENMASK_ULL(APL_ASYMSHIFT - 1, 0)); in apl_mk_region()
439 U64_LSHIFT(a->slice_asym_base, DNV_ASYMSHIFT), in dnv_mk_region()
440 U64_LSHIFT(a->slice_asym_limit, DNV_ASYMSHIFT) + in dnv_mk_region()
441 GENMASK_ULL(DNV_ASYMSHIFT - 1, 0)); in dnv_mk_region()
446 int ret = -ENODEV; in apl_get_registers()
450 return -ENODEV; in apl_get_registers()
453 * RD_REGP() will fail for unpopulated or non-existent in apl_get_registers()
468 return -ENODEV; in dnv_get_registers()
479 return -ENODEV; in dnv_get_registers()
501 return -ENODEV; in get_registers()
503 if (ops->get_registers()) in get_registers()
504 return -ENODEV; in get_registers()
506 if (ops->type == DNV) { in get_registers()
516 ops->mk_region("as0", &as0, &asym0); in get_registers()
519 ops->mk_region("as1", &as1, &asym1); in get_registers()
525 GENMASK_ULL(APL_ASYMSHIFT - 1, 0)); in get_registers()
590 return (sys < _4GB) ? sys : sys - (_4GB - top_lm); in remove_mmio_gap()
598 if (bitidx == -1) in remove_addr_bit()
601 mask = (1ull << bitidx) - 1; in remove_addr_bit()
640 * to do a 3-way interleave. in sys2pmi()
648 return -EINVAL; in sys2pmi()
658 contig_offset = contig_addr - contig_base; in sys2pmi()
666 contig_offset = contig_addr - contig_base; in sys2pmi()
681 contig_offset = contig_addr - contig_base; in sys2pmi()
908 struct pnd2_pvt *pvt = mci->pvt_info; in apl_pmi2mem()
909 int g = pvt->dimm_geom[pmiidx]; in apl_pmi2mem()
919 return -EINVAL; in apl_pmi2mem()
922 type = d->bits[i + skiprs] & ~0xf; in apl_pmi2mem()
923 idx = d->bits[i + skiprs] & 0xf; in apl_pmi2mem()
929 if (type == RS && (cr_drp0->rken0 + cr_drp0->rken1) == 1) { in apl_pmi2mem()
931 type = d->bits[i + skiprs] & ~0xf; in apl_pmi2mem()
932 idx = d->bits[i + skiprs] & 0xf; in apl_pmi2mem()
941 if (cr_drp0->bahen) in apl_pmi2mem()
942 bank ^= bank_hash(pmiaddr, idx, d->addrdec); in apl_pmi2mem()
949 if (cr_drp0->rsien) in apl_pmi2mem()
955 return -EINVAL; in apl_pmi2mem()
962 daddr->col = column; in apl_pmi2mem()
963 daddr->bank = bank; in apl_pmi2mem()
964 daddr->row = row; in apl_pmi2mem()
965 daddr->rank = rank; in apl_pmi2mem()
966 daddr->dimm = 0; in apl_pmi2mem()
978 daddr->rank = dnv_get_bit(pmiaddr, dmap[pmiidx].rs0 + 13, 0); in dnv_pmi2mem()
980 daddr->rank |= dnv_get_bit(pmiaddr, dmap[pmiidx].rs1 + 13, 1); in dnv_pmi2mem()
986 daddr->dimm = (daddr->rank >= 2) ^ drp[pmiidx].dimmflip; in dnv_pmi2mem()
988 daddr->bank = dnv_get_bit(pmiaddr, dmap[pmiidx].ba0 + 6, 0); in dnv_pmi2mem()
989 daddr->bank |= dnv_get_bit(pmiaddr, dmap[pmiidx].ba1 + 6, 1); in dnv_pmi2mem()
990 daddr->bank |= dnv_get_bit(pmiaddr, dmap[pmiidx].bg0 + 6, 2); in dnv_pmi2mem()
992 daddr->bank |= dnv_get_bit(pmiaddr, dmap[pmiidx].bg1 + 6, 3); in dnv_pmi2mem()
995 daddr->bank ^= dnv_get_bit(pmiaddr, dmap3[pmiidx].row6 + 6, 0); in dnv_pmi2mem()
996 daddr->bank ^= dnv_get_bit(pmiaddr, dmap3[pmiidx].row7 + 6, 1); in dnv_pmi2mem()
999 daddr->bank ^= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca3 + 6, 2); in dnv_pmi2mem()
1002 daddr->bank ^= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca4 + 6, 2); in dnv_pmi2mem()
1003 daddr->bank ^= dnv_get_bit(pmiaddr, dmap2[pmiidx].row2 + 6, 3); in dnv_pmi2mem()
1005 daddr->bank ^= dnv_get_bit(pmiaddr, dmap2[pmiidx].row2 + 6, 0); in dnv_pmi2mem()
1006 daddr->bank ^= dnv_get_bit(pmiaddr, dmap3[pmiidx].row6 + 6, 1); in dnv_pmi2mem()
1008 daddr->bank ^= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca3 + 6, 2); in dnv_pmi2mem()
1010 daddr->bank ^= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca4 + 6, 2); in dnv_pmi2mem()
1014 daddr->row = dnv_get_bit(pmiaddr, dmap2[pmiidx].row0 + 6, 0); in dnv_pmi2mem()
1015 daddr->row |= dnv_get_bit(pmiaddr, dmap2[pmiidx].row1 + 6, 1); in dnv_pmi2mem()
1016 daddr->row |= dnv_get_bit(pmiaddr, dmap2[pmiidx].row2 + 6, 2); in dnv_pmi2mem()
1017 daddr->row |= dnv_get_bit(pmiaddr, dmap2[pmiidx].row3 + 6, 3); in dnv_pmi2mem()
1018 daddr->row |= dnv_get_bit(pmiaddr, dmap2[pmiidx].row4 + 6, 4); in dnv_pmi2mem()
1019 daddr->row |= dnv_get_bit(pmiaddr, dmap2[pmiidx].row5 + 6, 5); in dnv_pmi2mem()
1020 daddr->row |= dnv_get_bit(pmiaddr, dmap3[pmiidx].row6 + 6, 6); in dnv_pmi2mem()
1021 daddr->row |= dnv_get_bit(pmiaddr, dmap3[pmiidx].row7 + 6, 7); in dnv_pmi2mem()
1022 daddr->row |= dnv_get_bit(pmiaddr, dmap3[pmiidx].row8 + 6, 8); in dnv_pmi2mem()
1023 daddr->row |= dnv_get_bit(pmiaddr, dmap3[pmiidx].row9 + 6, 9); in dnv_pmi2mem()
1024 daddr->row |= dnv_get_bit(pmiaddr, dmap3[pmiidx].row10 + 6, 10); in dnv_pmi2mem()
1025 daddr->row |= dnv_get_bit(pmiaddr, dmap3[pmiidx].row11 + 6, 11); in dnv_pmi2mem()
1026 daddr->row |= dnv_get_bit(pmiaddr, dmap4[pmiidx].row12 + 6, 12); in dnv_pmi2mem()
1027 daddr->row |= dnv_get_bit(pmiaddr, dmap4[pmiidx].row13 + 6, 13); in dnv_pmi2mem()
1029 daddr->row |= dnv_get_bit(pmiaddr, dmap4[pmiidx].row14 + 6, 14); in dnv_pmi2mem()
1031 daddr->row |= dnv_get_bit(pmiaddr, dmap4[pmiidx].row15 + 6, 15); in dnv_pmi2mem()
1033 daddr->row |= dnv_get_bit(pmiaddr, dmap4[pmiidx].row16 + 6, 16); in dnv_pmi2mem()
1035 daddr->row |= dnv_get_bit(pmiaddr, dmap4[pmiidx].row17 + 6, 17); in dnv_pmi2mem()
1037 daddr->col = dnv_get_bit(pmiaddr, dmap5[pmiidx].ca3 + 6, 3); in dnv_pmi2mem()
1038 daddr->col |= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca4 + 6, 4); in dnv_pmi2mem()
1039 daddr->col |= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca5 + 6, 5); in dnv_pmi2mem()
1040 daddr->col |= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca6 + 6, 6); in dnv_pmi2mem()
1041 daddr->col |= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca7 + 6, 7); in dnv_pmi2mem()
1042 daddr->col |= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca8 + 6, 8); in dnv_pmi2mem()
1043 daddr->col |= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca9 + 6, 9); in dnv_pmi2mem()
1045 daddr->col |= dnv_get_bit(pmiaddr, dmap1[pmiidx].ca11 + 13, 11); in dnv_pmi2mem()
1070 return ret ? -EINVAL : 0; in apl_check_ecc_active()
1073 #define DIMMS_PRESENT(d) ((d)->rken0 + (d)->rken1 + (d)->rken2 + (d)->rken3)
1092 return ret ? -EINVAL : 0; in dnv_check_ecc_active()
1106 pmiaddr >>= ops->pmiaddr_shift; in get_memory_error_data()
1108 pmiidx >>= ops->pmiidx_shift; in get_memory_error_data()
1109 daddr->chan = pmiidx; in get_memory_error_data()
1111 ret = ops->pmi2mem(mci, pmiaddr, pmiidx, daddr, msg); in get_memory_error_data()
1116 addr, pmiaddr, daddr->chan, daddr->dimm, daddr->rank, daddr->bank, daddr->row, daddr->col); in get_memory_error_data()
1126 bool ripv = m->mcgstatus & MCG_STATUS_RIPV; in pnd2_mce_output_error()
1127 bool overflow = m->status & MCI_STATUS_OVER; in pnd2_mce_output_error()
1128 bool uc_err = m->status & MCI_STATUS_UC; in pnd2_mce_output_error()
1129 bool recov = m->status & MCI_STATUS_S; in pnd2_mce_output_error()
1130 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); in pnd2_mce_output_error()
1131 u32 mscod = GET_BITFIELD(m->status, 16, 31); in pnd2_mce_output_error()
1132 u32 errcode = GET_BITFIELD(m->status, 0, 15); in pnd2_mce_output_error()
1133 u32 optypenum = GET_BITFIELD(m->status, 4, 6); in pnd2_mce_output_error()
1140 * According with Table 15-9 of the Intel Architecture spec vol 3A, in pnd2_mce_output_error()
1176 if (!(m->status & MCI_STATUS_ADDRV)) in pnd2_mce_output_error()
1179 rc = get_memory_error_data(mci, m->addr, daddr, msg); in pnd2_mce_output_error()
1186 errcode, daddr->chan, daddr->dimm, daddr->rank, daddr->row, daddr->bank, daddr->col); in pnd2_mce_output_error()
1191 edac_mc_handle_error(tp_event, mci, core_err_cnt, m->addr >> PAGE_SHIFT, in pnd2_mce_output_error()
1192 m->addr & ~PAGE_MASK, 0, daddr->chan, daddr->dimm, -1, optype, msg); in pnd2_mce_output_error()
1197 edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0, -1, -1, -1, msg, ""); in pnd2_mce_output_error()
1202 struct pnd2_pvt *pvt = mci->pvt_info; in apl_get_dimm_config()
1220 if (dimms[g].addrdec == d->addrdec && in apl_get_dimm_config()
1221 dimms[g].dden == d->dden && in apl_get_dimm_config()
1222 dimms[g].dwid == d->dwid) in apl_get_dimm_config()
1230 pvt->dimm_geom[i] = g; in apl_get_dimm_config()
1231 capacity = (d->rken0 + d->rken1) * 8 * (1ul << dimms[g].rowbits) * in apl_get_dimm_config()
1233 edac_dbg(0, "Channel %d: %lld MByte DIMM\n", i, capacity >> (20 - 3)); in apl_get_dimm_config()
1234 dimm->nr_pages = MiB_TO_PAGES(capacity >> (20 - 3)); in apl_get_dimm_config()
1235 dimm->grain = 32; in apl_get_dimm_config()
1236 dimm->dtype = (d->dwid == 0) ? DEV_X8 : DEV_X16; in apl_get_dimm_config()
1237 dimm->mtype = MEM_DDR3; in apl_get_dimm_config()
1238 dimm->edac_mode = EDAC_SECDED; in apl_get_dimm_config()
1239 snprintf(dimm->label, sizeof(dimm->label), "Slice#%d_Chan#%d", i / 2, i % 2); in apl_get_dimm_config()
1284 ranks_of_dimm[0] = d->rken0 + d->rken1; in dnv_get_dimm_config()
1286 ranks_of_dimm[1] = d->rken2 + d->rken3; in dnv_get_dimm_config()
1299 edac_dbg(0, "Channel %d DIMM %d: %lld MByte DIMM\n", i, j, capacity >> (20 - 3)); in dnv_get_dimm_config()
1300 dimm->nr_pages = MiB_TO_PAGES(capacity >> (20 - 3)); in dnv_get_dimm_config()
1301 dimm->grain = 32; in dnv_get_dimm_config()
1302 dimm->dtype = dnv_dtypes[j ? d->dimmdwid0 : d->dimmdwid1]; in dnv_get_dimm_config()
1303 dimm->mtype = memtype; in dnv_get_dimm_config()
1304 dimm->edac_mode = EDAC_SECDED; in dnv_get_dimm_config()
1305 snprintf(dimm->label, sizeof(dimm->label), "Chan#%d_DIMM#%d", i, j); in dnv_get_dimm_config()
1317 rc = ops->check_ecc(); in pnd2_register_mci()
1323 layers[0].size = ops->channels; in pnd2_register_mci()
1326 layers[1].size = ops->dimms_per_channel; in pnd2_register_mci()
1330 return -ENOMEM; in pnd2_register_mci()
1332 pvt = mci->pvt_info; in pnd2_register_mci()
1335 mci->mod_name = EDAC_MOD_STR; in pnd2_register_mci()
1336 mci->dev_name = ops->name; in pnd2_register_mci()
1337 mci->ctl_name = "Pondicherry2"; in pnd2_register_mci()
1340 ops->get_dimm_config(mci); in pnd2_register_mci()
1345 return -EINVAL; in pnd2_register_mci()
1355 if (unlikely(!mci || !mci->pvt_info)) { in pnd2_unregister_mci()
1362 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); in pnd2_unregister_mci()
1378 if (!mci || (mce->kflags & MCE_HANDLED_CEC)) in pnd2_mce_check_error()
1384 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0. in pnd2_mce_check_error()
1387 if ((mce->status & 0xefff) >> 7 != 1) in pnd2_mce_check_error()
1390 if (mce->mcgstatus & MCG_STATUS_MCIP) in pnd2_mce_check_error()
1397 mce->extcpu, type, mce->mcgstatus, mce->bank, mce->status); in pnd2_mce_check_error()
1398 pnd2_mc_printk(mci, KERN_INFO, "TSC %llx ", mce->tsc); in pnd2_mce_check_error()
1399 pnd2_mc_printk(mci, KERN_INFO, "ADDR %llx ", mce->addr); in pnd2_mce_check_error()
1400 pnd2_mc_printk(mci, KERN_INFO, "MISC %llx ", mce->misc); in pnd2_mce_check_error()
1402 mce->cpuvendor, mce->cpuid, mce->time, mce->socketid, mce->apicid); in pnd2_mce_check_error()
1407 mce->kflags |= MCE_HANDLED_EDAC; in pnd2_mce_check_error()
1532 return -EBUSY; in pnd2_init()
1536 return -EBUSY; in pnd2_init()
1539 return -ENODEV; in pnd2_init()
1543 return -ENODEV; in pnd2_init()
1545 ops = (struct dunit_ops *)id->driver_data; in pnd2_init()
1547 if (ops->type == APL) { in pnd2_init()
1550 return -ENODEV; in pnd2_init()
1563 return -ENODEV; in pnd2_init()