1 // SPDX-License-Identifier: GPL-2.0-only
71 	"PFB non-cacheable bit parity error",
77 	"fetch address FIFO",
84 	"Prefetcher request FIFO parity error",
101 	"Link-defined sync error packets detected on HT link",
138 	"Hardware Assertion",
174 	"An ECC error was detected on a data cache read-modify-write by a store",
179 	"An ECC error was detected on an EMEM read-modify-write by a store",
194 	"A hardware assertion error was reported",
200 	"IC Microtag or Full Tag Multi-hit Error",
209 	"L1 BTB Multi-Match Error",
210 	"L2 BTB Multi-Match Error",
213 	"Hardware Assertion Error",
214 	"L1-TLB Multi-Hit",
215 	"L2-TLB Multi-Hit",
221 	"L2M Tag Multiple-Way-Hit error",
224 	"Hardware Assert Error",
228 	"Micro-op cache tag parity error",
229 	"Micro-op cache data parity error",
231 	"Micro-op queue parity error",
233 	"Fetch address FIFO parity error",
236 	"Micro-op buffer parity error",
237 	"Hardware Assertion MCA Error",
252 	"Hardware Assertion error",
264 	"Hardware assertion",
269 	"Shadow Tag Macro Multi-way-hit Error",
271 	"L3M Tag Multi-way-hit Error",
275 	"L3 Hardware Assertion",
308 	"Hardware Assert",
446 	"MPDMA PTE Command FIFO ECC or parity error",
447 	"MPDMA PTE Hub Data FIFO ECC or parity error",
448 	"MPDMA PTE Internal Data FIFO ECC or parity error",
451 	"MPDMA PTE DMA Completion FIFO ECC or parity error",
452 	"MPDMA PTE Tablewalk Completion FIFO ECC or parity error",
453 	"MPDMA PTE Descriptor Completion FIFO ECC or parity error",
454 	"MPDMA PTE ReadOnly Completion FIFO ECC or parity error",
455 	"MPDMA PTE DirectWrite Completion FIFO ECC or parity error",
469 	"CCIX Read Response with Status: Non-Data Error",
470 	"CCIX Write Response with Status: Non-Data Error",
472 	"CCIX Non-okay write response with data error",
483 	"Rx Fifo Underflow Error",
484 	"Rx Fifo Overflow Error",
490 	"Replay Fifo Overflow Error",
491 	"Replay Fifo Underflow Error",
492 	"Elastic Fifo Overflow Error",
549 	"Rx Fifo Underflow Error",
550 	"Rx Fifo Overflow Error",
553 	"Tx Fifo Underflow Error",
556 	"Replay Fifo Overflow Error",
557 	"Replay Fifo Underflow Error",
558 	"Elastic Fifo Overflow Error",
570 	"Rx LFDS Fifo Overflow Error",
571 	"Rx LFDS Fifo Underflow Error",
754 			pr_cont("Hardware Assert.\n");  in f15h_mc0_mce()
766 	u16 ec = EC(m->status);  in decode_mc0_mce()
767 	u8 xec = XEC(m->status, xec_mask);  in decode_mc0_mce()
857 		pr_cont("%s.\n", f15h_mc1_mce_desc[xec-2]);  in f15h_mc1_mce()
861 		pr_cont("%s.\n", f15h_mc1_mce_desc[xec-4]);  in f15h_mc1_mce()
865 		pr_cont("Decoder %s parity error.\n", f15h_mc1_mce_desc[xec-4]);  in f15h_mc1_mce()
876 	u16 ec = EC(m->status);  in decode_mc1_mce()
877 	u8 xec = XEC(m->status, xec_mask);  in decode_mc1_mce()
885 		bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58)));  in decode_mc1_mce()
890 			pr_cont("Hardware Assert.\n");  in decode_mc1_mce()
959 			pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x4]);  in f15h_mc2_mce()
963 			pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x7]);  in f15h_mc2_mce()
971 			pr_cont("Hardware Assert.\n");  in f15h_mc2_mce()
1022 	u16 ec = EC(m->status);  in decode_mc2_mce()
1023 	u8 xec = XEC(m->status, xec_mask);  in decode_mc2_mce()
1033 	u16 ec = EC(m->status);  in decode_mc3_mce()
1034 	u8 xec = XEC(m->status, xec_mask);  in decode_mc3_mce()
1062 	unsigned int fam = x86_family(m->cpuid);  in decode_mc4_mce()
1063 	int node_id = topology_die_id(m->extcpu);  in decode_mc4_mce()
1064 	u16 ec = EC(m->status);  in decode_mc4_mce()
1065 	u8 xec = XEC(m->status, 0x1f);  in decode_mc4_mce()
1111 	pr_cont("%s.\n", mc4_mce_desc[xec - offset]);  in decode_mc4_mce()
1120 	unsigned int fam = x86_family(m->cpuid);  in decode_mc5_mce()
1121 	u16 ec = EC(m->status);  in decode_mc5_mce()
1122 	u8 xec = XEC(m->status, xec_mask);  in decode_mc5_mce()
1131 			pr_cont("Hardware Assert.\n");  in decode_mc5_mce()
1152 	u8 xec = XEC(m->status, xec_mask);  in decode_mc6_mce()
1169 	enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank);  in decode_smca_error()
1171 	u8 xec = XEC(m->status, xec_mask);  in decode_smca_error()
1177 		pr_emerg(HW_ERR "Bank %d is reserved.\n", m->bank);  in decode_smca_error()
1191 		decode_dram_ecc(topology_die_id(m->extcpu), m);  in decode_smca_error()
1209 		pr_cont(", mem-tx: %s", R4_MSG(ec));  in amd_decode_err_code()
1212 			pr_cont(", part-proc: %s (%s)", PP_MSG(ec), TO_MSG(ec));  in amd_decode_err_code()
1220 	if (m->status & MCI_STATUS_UC) {  in decode_error_status()
1221 		if (m->status & MCI_STATUS_PCC)  in decode_error_status()
1223 		if (m->mcgstatus & MCG_STATUS_RIPV)  in decode_error_status()
1228 	if (m->status & MCI_STATUS_DEFERRED)  in decode_error_status()
1238 	unsigned int fam = x86_family(m->cpuid);  in amd_decode_mce()
1241 	if (m->kflags & MCE_HANDLED_CEC)  in amd_decode_mce()
1247 		m->extcpu,  in amd_decode_mce()
1248 		fam, x86_model(m->cpuid), x86_stepping(m->cpuid),  in amd_decode_mce()
1249 		m->bank,  in amd_decode_mce()
1250 		((m->status & MCI_STATUS_OVER)	? "Over"  : "-"),  in amd_decode_mce()
1251 		((m->status & MCI_STATUS_UC)	? "UE"	  :  in amd_decode_mce()
1252 		 (m->status & MCI_STATUS_DEFERRED) ? "-"  : "CE"),  in amd_decode_mce()
1253 		((m->status & MCI_STATUS_MISCV)	? "MiscV" : "-"),  in amd_decode_mce()
1254 		((m->status & MCI_STATUS_ADDRV)	? "AddrV" : "-"),  in amd_decode_mce()
1255 		((m->status & MCI_STATUS_PCC)	? "PCC"	  : "-"));  in amd_decode_mce()
1259 		u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank);  in amd_decode_mce()
1263 			pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-"));  in amd_decode_mce()
1265 		pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-"));  in amd_decode_mce()
1269 	ecc = (m->status >> 45) & 0x3;  in amd_decode_mce()
1274 		pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : "-"));  in amd_decode_mce()
1277 		if (fam != 0x15 || m->bank != 4)  in amd_decode_mce()
1278 			pr_cont("|%s", (m->status & MCI_STATUS_POISON ? "Poison" : "-"));  in amd_decode_mce()
1282 		pr_cont("|%s", (m->status & MCI_STATUS_SCRUB ? "Scrub" : "-"));  in amd_decode_mce()
1284 	pr_cont("]: 0x%016llx\n", m->status);  in amd_decode_mce()
1286 	if (m->status & MCI_STATUS_ADDRV)  in amd_decode_mce()
1287 		pr_emerg(HW_ERR "Error Addr: 0x%016llx\n", m->addr);  in amd_decode_mce()
1289 	if (m->ppin)  in amd_decode_mce()
1290 		pr_emerg(HW_ERR "PPIN: 0x%016llx\n", m->ppin);  in amd_decode_mce()
1293 		pr_emerg(HW_ERR "IPID: 0x%016llx", m->ipid);  in amd_decode_mce()
1295 		if (m->status & MCI_STATUS_SYNDV)  in amd_decode_mce()
1296 			pr_cont(", Syndrome: 0x%016llx", m->synd);  in amd_decode_mce()
1304 	if (m->tsc)  in amd_decode_mce()
1305 		pr_emerg(HW_ERR "TSC: %llu\n", m->tsc);  in amd_decode_mce()
1311 	switch (m->bank) {  in amd_decode_mce()
1345 	amd_decode_err_code(m->status & 0xffff);  in amd_decode_mce()
1347 	m->kflags |= MCE_HANDLED_EDAC;  in amd_decode_mce()
1360 	if (c->x86_vendor != X86_VENDOR_AMD &&  in mce_amd_init()
1361 	    c->x86_vendor != X86_VENDOR_HYGON)  in mce_amd_init()
1362 		return -ENODEV;  in mce_amd_init()
1365 		return -ENODEV;  in mce_amd_init()
1372 	switch (c->x86) {  in mce_amd_init()
1404 		xec_mask = c->x86_model == 0x60 ? 0x3f : 0x1f;  in mce_amd_init()
1421 		return -EINVAL;  in mce_amd_init()
1424 		printk(KERN_WARNING "Huh? What family is it: 0x%x?!\n", c->x86);  in mce_amd_init()
1425 		return -EINVAL;  in mce_amd_init()
1429 	pr_info("MCE: In-kernel MCE decoding enabled.\n");  in mce_amd_init()
1444 MODULE_ALIAS("edac-mce-amd");