178 static u32 dmc520_read_reg(struct dmc520_edac *pvt, u32 offset)  in dmc520_read_reg()  function
212 	err_low = dmc520_read_reg(pvt, reg_offset_low);  in dmc520_get_dram_ecc_error_count()
213 	err_high = dmc520_read_reg(pvt, reg_offset_high);  in dmc520_get_dram_ecc_error_count()
237 	reg_val_low = dmc520_read_reg(pvt, reg_offset_low);  in dmc520_get_dram_ecc_error_info()
238 	reg_val_high = dmc520_read_reg(pvt, reg_offset_high);  in dmc520_get_dram_ecc_error_info()
265 	reg_val = dmc520_read_reg(pvt, REG_OFFSET_SCRUB_CONTROL0_NOW);  in dmc520_get_scrub_type()
282 	reg_val = dmc520_read_reg(pvt, REG_OFFSET_FORMAT_CONTROL);  in dmc520_get_memory_width()
298 	reg_val = dmc520_read_reg(pvt, REG_OFFSET_MEMORY_TYPE_NOW);  in dmc520_get_mtype()
320 	reg_val = dmc520_read_reg(pvt, REG_OFFSET_MEMORY_TYPE_NOW);  in dmc520_get_dtype()
354 	reg_val = dmc520_read_reg(pvt, REG_OFFSET_ADDRESS_CONTROL_NOW);  in dmc520_get_rank_size()
414 	status = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_STATUS);  in dmc520_edac_dram_all_isr()
554 	reg_val = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_CONTROL);  in dmc520_edac_probe()
615 	reg_val = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_CONTROL);  in dmc520_edac_remove()