Lines Matching full:on
14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS
38 This turns on debugging information for the entire EDAC subsystem.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
45 depends on CPU_SUP_AMD && X86_MCE_AMD
49 occurring on your machine in human-readable form.
57 depends on ACPI_APEI_GHES
80 depends on AMD_NB && EDAC_DECODE_MCE
82 Support for error detection and correction of DRAM ECC errors on
105 depends on (ARCH_ALPINE || COMPILE_TEST)
112 depends on PCI && X86_32
114 Support for error detection and correction on the AMD 76x
119 depends on PCI && X86_32
121 Support for error detection and correction on the Intel
126 depends on PCI && X86
128 Support for error detection and correction on the Intel
133 depends on PCI && X86_32
134 depends on BROKEN
136 Support for error detection and correction on the Intel
141 depends on PCI && X86_32
143 Support for error detection and correction on the Intel
148 depends on PCI && X86
150 Support for error detection and correction on the Intel
155 depends on PCI && X86
157 Support for error detection and correction on the Intel
162 depends on PCI && X86
164 Support for error detection and correction on the Intel
169 depends on PCI && X86
171 Support for error detection and correction on the Intel
176 depends on PCI && X86
178 Support for error detection and correction on the Intel
183 depends on PCI && X86
190 depends on PCI && X86 && X86_MCE_INTEL
193 i7 Core (Nehalem) Integrated Memory Controller that exists on
199 depends on PCI && X86_32
201 Support for error detection and correction on the Intel
206 depends on PCI && X86_32
208 Support for error detection and correction on the Radisys
213 depends on X86 && PCI
214 depends on BROKEN
221 depends on X86 && PCI
228 depends on X86 && PCI
235 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
242 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
243 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
254 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
255 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y
266 depends on PCI && X86_64 && X86_MCE_INTEL
269 Support for error detection and correction on the Intel
271 first used on the Apollo Lake platform and Denverton
272 micro-server but may appear on others in the future.
276 depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG
277 depends on X86_64 && X86_MCE_INTEL
279 Support for error detection and correction on the Intel
281 This In-Band ECC is first used on the Elkhart Lake SoC but
282 may appear on others in the future.
286 depends on FSL_SOC && EDAC=y
288 Support for error detection and correction on the Freescale
293 depends on ARCH_LAYERSCAPE || SOC_LS1021A
295 Support for error detection and correction on Freescale memory
296 controllers on Layerscape SoCs.
300 depends on PPC_PASEMI && PCI
302 Support for error detection and correction on PA Semi
307 depends on PPC_CELL_COMMON
309 Support for error detection and correction on the
311 on platform without a hypervisor
315 depends on 4xx
317 This enables support for EDAC on the ECC memory used
324 depends on PCI && PPC_MAPLE
326 Support for error detection and correction on the
329 on some machine other than Maple.
333 depends on PCI && PPC_MAPLE
335 Support for error detection and correction on the
338 on some machine other than Maple.
342 depends on PPC64
344 Support for error detection and correction on the
351 depends on ARCH_HIGHBANK
353 Support for error detection and correction on the
358 depends on ARCH_HIGHBANK
360 Support for error detection and correction on the
365 depends on CPU_CAVIUM_OCTEON
367 Support for error detection and correction on the primary caches of
372 depends on CAVIUM_OCTEON_SOC
374 Support for error detection and correction on the
379 depends on CAVIUM_OCTEON_SOC
381 Support for error detection and correction on the
386 depends on PCI && CAVIUM_OCTEON_SOC
388 Support for error detection and correction on the
393 depends on ARM64
394 depends on PCI
396 Support for error detection and correction on the
403 depends on EDAC=y && ARCH_INTEL_SOCFPGA
405 Support for error detection and correction on the
411 depends on EDAC_ALTERA=y
413 Support for error detection and correction on the
420 depends on EDAC_ALTERA=y && CACHE_L2X0
422 Support for error detection and correction on the
427 bool "Altera On-Chip RAM ECC"
428 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
430 Support for error detection and correction on the
431 Altera On-Chip RAM Memory for Altera SoCs.
435 depends on EDAC_ALTERA=y
437 Support for error detection and correction on the
442 depends on EDAC_ALTERA=y && MTD_NAND_DENALI
444 Support for error detection and correction on the
449 depends on EDAC_ALTERA=y && PL330_DMA=y
451 Support for error detection and correction on the
456 depends on EDAC_ALTERA=y && USB_DWC2
458 Support for error detection and correction on the
463 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
465 Support for error detection and correction on the
470 depends on EDAC_ALTERA=y && MMC_DW
472 Support for error detection and correction on the
477 depends on EDAC=y && SIFIVE_CCACHE
479 Support for error detection and correction on the SiFive SoCs.
483 depends on MACH_MVEBU_V7
485 Support for error correction and detection on the Marvell Aramada XP
490 depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC
492 Support for error detection and correction on the Synopsys DDR
497 depends on (ARM64 || COMPILE_TEST)
499 Support for error detection and correction on the
504 depends on ARCH_KEYSTONE || SOC_DRA7XX
506 Support for error detection and correction on the TI SoCs.
510 depends on ARCH_QCOM && QCOM_LLCC
512 Support for error detection and correction on the
524 depends on ARCH_ASPEED
526 Support for error detection and correction on the Aspeed AST BMC SoC.
533 depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST)
535 Support for error detection and correction on the
540 depends on ARM64
542 Support for error detection and correction on the
547 depends on ARCH_ZYNQMP || COMPILE_TEST
550 Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be
555 depends on (ARCH_NPCM || COMPILE_TEST)
557 Support for error detection and correction on the Nuvoton NPCM DDR