Lines Matching +full:zynqmp +full:- +full:8
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DMA driver for Xilinx ZynqMP DMA Engine
9 #include <linux/dma-mapping.h>
19 #include <linux/io-64-nonatomic-lo-hi.h>
54 #define ZYNQMP_DMA_AXI_RD_DATA BIT(8)
80 #define ZYNQMP_DMA_AWCACHE GENMASK(11, 8)
81 #define ZYNQMP_DMA_AWCACHE_OFST 8
88 #define ZYNQMP_DMA_AXCOHRNT BIT(8)
141 #define ZYNQMP_DMA_DESC_SIZE(chan) (chan->desc_size)
149 * struct zynqmp_dma_desc_ll - Hw linked list descriptor
165 * struct zynqmp_dma_desc_sw - Per Transaction structure
191 * struct zynqmp_dma_chan - Driver specific DMA channel structure
241 * struct zynqmp_dma_device - DMA device structure
259 lo_hi_writeq(value, chan->regs + reg); in zynqmp_dma_writeq()
263 * zynqmp_dma_update_desc_to_ctrlr - Updates descriptor to the controller
264 * @chan: ZynqMP DMA DMA channel pointer
272 addr = desc->src_p; in zynqmp_dma_update_desc_to_ctrlr()
274 addr = desc->dst_p; in zynqmp_dma_update_desc_to_ctrlr()
279 * zynqmp_dma_desc_config_eod - Mark the descriptor as end descriptor
280 * @chan: ZynqMP DMA channel pointer
288 hw->ctrl |= ZYNQMP_DMA_DESC_CTRL_STOP; in zynqmp_dma_desc_config_eod()
290 hw->ctrl |= ZYNQMP_DMA_DESC_CTRL_COMP_INT | ZYNQMP_DMA_DESC_CTRL_STOP; in zynqmp_dma_desc_config_eod()
294 * zynqmp_dma_config_sg_ll_desc - Configure the linked list descriptor
295 * @chan: ZynqMP DMA channel pointer
309 sdesc->size = ddesc->size = len; in zynqmp_dma_config_sg_ll_desc()
310 sdesc->addr = src; in zynqmp_dma_config_sg_ll_desc()
311 ddesc->addr = dst; in zynqmp_dma_config_sg_ll_desc()
313 sdesc->ctrl = ddesc->ctrl = ZYNQMP_DMA_DESC_CTRL_SIZE_256; in zynqmp_dma_config_sg_ll_desc()
314 if (chan->is_dmacoherent) { in zynqmp_dma_config_sg_ll_desc()
315 sdesc->ctrl |= ZYNQMP_DMA_DESC_CTRL_COHRNT; in zynqmp_dma_config_sg_ll_desc()
316 ddesc->ctrl |= ZYNQMP_DMA_DESC_CTRL_COHRNT; in zynqmp_dma_config_sg_ll_desc()
320 dma_addr_t addr = chan->desc_pool_p + in zynqmp_dma_config_sg_ll_desc()
321 ((uintptr_t)sdesc - (uintptr_t)chan->desc_pool_v); in zynqmp_dma_config_sg_ll_desc()
323 prev->nxtdscraddr = addr; in zynqmp_dma_config_sg_ll_desc()
324 ddesc->nxtdscraddr = addr + ZYNQMP_DMA_DESC_SIZE(chan); in zynqmp_dma_config_sg_ll_desc()
329 * zynqmp_dma_init - Initialize the channel
330 * @chan: ZynqMP DMA channel pointer
336 writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS); in zynqmp_dma_init()
337 val = readl(chan->regs + ZYNQMP_DMA_ISR); in zynqmp_dma_init()
338 writel(val, chan->regs + ZYNQMP_DMA_ISR); in zynqmp_dma_init()
340 if (chan->is_dmacoherent) { in zynqmp_dma_init()
344 writel(val, chan->regs + ZYNQMP_DMA_DSCR_ATTR); in zynqmp_dma_init()
347 val = readl(chan->regs + ZYNQMP_DMA_DATA_ATTR); in zynqmp_dma_init()
348 if (chan->is_dmacoherent) { in zynqmp_dma_init()
354 writel(val, chan->regs + ZYNQMP_DMA_DATA_ATTR); in zynqmp_dma_init()
357 val = readl(chan->regs + ZYNQMP_DMA_IRQ_SRC_ACCT); in zynqmp_dma_init()
358 val = readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT); in zynqmp_dma_init()
360 chan->idle = true; in zynqmp_dma_init()
364 * zynqmp_dma_tx_submit - Submit DMA transaction
371 struct zynqmp_dma_chan *chan = to_chan(tx->chan); in zynqmp_dma_tx_submit()
377 spin_lock_irqsave(&chan->lock, irqflags); in zynqmp_dma_tx_submit()
380 if (!list_empty(&chan->pending_list)) { in zynqmp_dma_tx_submit()
381 desc = list_last_entry(&chan->pending_list, in zynqmp_dma_tx_submit()
383 if (!list_empty(&desc->tx_list)) in zynqmp_dma_tx_submit()
384 desc = list_last_entry(&desc->tx_list, in zynqmp_dma_tx_submit()
386 desc->src_v->nxtdscraddr = new->src_p; in zynqmp_dma_tx_submit()
387 desc->src_v->ctrl &= ~ZYNQMP_DMA_DESC_CTRL_STOP; in zynqmp_dma_tx_submit()
388 desc->dst_v->nxtdscraddr = new->dst_p; in zynqmp_dma_tx_submit()
389 desc->dst_v->ctrl &= ~ZYNQMP_DMA_DESC_CTRL_STOP; in zynqmp_dma_tx_submit()
392 list_add_tail(&new->node, &chan->pending_list); in zynqmp_dma_tx_submit()
393 spin_unlock_irqrestore(&chan->lock, irqflags); in zynqmp_dma_tx_submit()
399 * zynqmp_dma_get_descriptor - Get the sw descriptor from the pool
400 * @chan: ZynqMP DMA channel pointer
410 spin_lock_irqsave(&chan->lock, irqflags); in zynqmp_dma_get_descriptor()
411 desc = list_first_entry(&chan->free_list, in zynqmp_dma_get_descriptor()
413 list_del(&desc->node); in zynqmp_dma_get_descriptor()
414 spin_unlock_irqrestore(&chan->lock, irqflags); in zynqmp_dma_get_descriptor()
416 INIT_LIST_HEAD(&desc->tx_list); in zynqmp_dma_get_descriptor()
418 memset((void *)desc->src_v, 0, ZYNQMP_DMA_DESC_SIZE(chan)); in zynqmp_dma_get_descriptor()
419 memset((void *)desc->dst_v, 0, ZYNQMP_DMA_DESC_SIZE(chan)); in zynqmp_dma_get_descriptor()
425 * zynqmp_dma_free_descriptor - Issue pending transactions
426 * @chan: ZynqMP DMA channel pointer
434 chan->desc_free_cnt++; in zynqmp_dma_free_descriptor()
435 list_move_tail(&sdesc->node, &chan->free_list); in zynqmp_dma_free_descriptor()
436 list_for_each_entry_safe(child, next, &sdesc->tx_list, node) { in zynqmp_dma_free_descriptor()
437 chan->desc_free_cnt++; in zynqmp_dma_free_descriptor()
438 list_move_tail(&child->node, &chan->free_list); in zynqmp_dma_free_descriptor()
443 * zynqmp_dma_free_desc_list - Free descriptors list
444 * @chan: ZynqMP DMA channel pointer
457 * zynqmp_dma_alloc_chan_resources - Allocate channel resources
468 ret = pm_runtime_resume_and_get(chan->dev); in zynqmp_dma_alloc_chan_resources()
472 chan->sw_desc_pool = kcalloc(ZYNQMP_DMA_NUM_DESCS, sizeof(*desc), in zynqmp_dma_alloc_chan_resources()
474 if (!chan->sw_desc_pool) in zynqmp_dma_alloc_chan_resources()
475 return -ENOMEM; in zynqmp_dma_alloc_chan_resources()
477 chan->idle = true; in zynqmp_dma_alloc_chan_resources()
478 chan->desc_free_cnt = ZYNQMP_DMA_NUM_DESCS; in zynqmp_dma_alloc_chan_resources()
480 INIT_LIST_HEAD(&chan->free_list); in zynqmp_dma_alloc_chan_resources()
483 desc = chan->sw_desc_pool + i; in zynqmp_dma_alloc_chan_resources()
484 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in zynqmp_dma_alloc_chan_resources()
485 desc->async_tx.tx_submit = zynqmp_dma_tx_submit; in zynqmp_dma_alloc_chan_resources()
486 list_add_tail(&desc->node, &chan->free_list); in zynqmp_dma_alloc_chan_resources()
489 chan->desc_pool_v = dma_alloc_coherent(chan->dev, in zynqmp_dma_alloc_chan_resources()
492 &chan->desc_pool_p, GFP_KERNEL); in zynqmp_dma_alloc_chan_resources()
493 if (!chan->desc_pool_v) in zynqmp_dma_alloc_chan_resources()
494 return -ENOMEM; in zynqmp_dma_alloc_chan_resources()
497 desc = chan->sw_desc_pool + i; in zynqmp_dma_alloc_chan_resources()
498 desc->src_v = (struct zynqmp_dma_desc_ll *) (chan->desc_pool_v + in zynqmp_dma_alloc_chan_resources()
500 desc->dst_v = (struct zynqmp_dma_desc_ll *) (desc->src_v + 1); in zynqmp_dma_alloc_chan_resources()
501 desc->src_p = chan->desc_pool_p + in zynqmp_dma_alloc_chan_resources()
503 desc->dst_p = desc->src_p + ZYNQMP_DMA_DESC_SIZE(chan); in zynqmp_dma_alloc_chan_resources()
510 * zynqmp_dma_start - Start DMA channel
511 * @chan: ZynqMP DMA channel pointer
515 writel(ZYNQMP_DMA_INT_EN_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IER); in zynqmp_dma_start()
516 writel(0, chan->regs + ZYNQMP_DMA_TOTAL_BYTE); in zynqmp_dma_start()
517 chan->idle = false; in zynqmp_dma_start()
518 writel(ZYNQMP_DMA_ENABLE, chan->regs + ZYNQMP_DMA_CTRL2); in zynqmp_dma_start()
522 * zynqmp_dma_handle_ovfl_int - Process the overflow interrupt
523 * @chan: ZynqMP DMA channel pointer
529 writel(0, chan->regs + ZYNQMP_DMA_TOTAL_BYTE); in zynqmp_dma_handle_ovfl_int()
531 readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT); in zynqmp_dma_handle_ovfl_int()
533 readl(chan->regs + ZYNQMP_DMA_IRQ_SRC_ACCT); in zynqmp_dma_handle_ovfl_int()
540 val = readl(chan->regs + ZYNQMP_DMA_CTRL0); in zynqmp_dma_config()
542 writel(val, chan->regs + ZYNQMP_DMA_CTRL0); in zynqmp_dma_config()
544 val = readl(chan->regs + ZYNQMP_DMA_DATA_ATTR); in zynqmp_dma_config()
545 burst_val = __ilog2_u32(chan->src_burst_len); in zynqmp_dma_config()
548 burst_val = __ilog2_u32(chan->dst_burst_len); in zynqmp_dma_config()
551 writel(val, chan->regs + ZYNQMP_DMA_DATA_ATTR); in zynqmp_dma_config()
555 * zynqmp_dma_device_config - Zynqmp dma device configuration
566 chan->src_burst_len = clamp(config->src_maxburst, 1U, in zynqmp_dma_device_config()
568 chan->dst_burst_len = clamp(config->dst_maxburst, 1U, in zynqmp_dma_device_config()
575 * zynqmp_dma_start_transfer - Initiate the new transfer
576 * @chan: ZynqMP DMA channel pointer
582 if (!chan->idle) in zynqmp_dma_start_transfer()
587 desc = list_first_entry_or_null(&chan->pending_list, in zynqmp_dma_start_transfer()
592 list_splice_tail_init(&chan->pending_list, &chan->active_list); in zynqmp_dma_start_transfer()
599 * zynqmp_dma_chan_desc_cleanup - Cleanup the completed descriptors
600 * @chan: ZynqMP DMA channel
607 spin_lock_irqsave(&chan->lock, irqflags); in zynqmp_dma_chan_desc_cleanup()
609 list_for_each_entry_safe(desc, next, &chan->done_list, node) { in zynqmp_dma_chan_desc_cleanup()
612 dmaengine_desc_get_callback(&desc->async_tx, &cb); in zynqmp_dma_chan_desc_cleanup()
614 spin_unlock_irqrestore(&chan->lock, irqflags); in zynqmp_dma_chan_desc_cleanup()
616 spin_lock_irqsave(&chan->lock, irqflags); in zynqmp_dma_chan_desc_cleanup()
623 spin_unlock_irqrestore(&chan->lock, irqflags); in zynqmp_dma_chan_desc_cleanup()
627 * zynqmp_dma_complete_descriptor - Mark the active descriptor as complete
628 * @chan: ZynqMP DMA channel pointer
634 desc = list_first_entry_or_null(&chan->active_list, in zynqmp_dma_complete_descriptor()
638 list_del(&desc->node); in zynqmp_dma_complete_descriptor()
639 dma_cookie_complete(&desc->async_tx); in zynqmp_dma_complete_descriptor()
640 list_add_tail(&desc->node, &chan->done_list); in zynqmp_dma_complete_descriptor()
644 * zynqmp_dma_issue_pending - Issue pending transactions
652 spin_lock_irqsave(&chan->lock, irqflags); in zynqmp_dma_issue_pending()
654 spin_unlock_irqrestore(&chan->lock, irqflags); in zynqmp_dma_issue_pending()
658 * zynqmp_dma_free_descriptors - Free channel descriptors
659 * @chan: ZynqMP DMA channel pointer
665 spin_lock_irqsave(&chan->lock, irqflags); in zynqmp_dma_free_descriptors()
666 zynqmp_dma_free_desc_list(chan, &chan->active_list); in zynqmp_dma_free_descriptors()
667 zynqmp_dma_free_desc_list(chan, &chan->pending_list); in zynqmp_dma_free_descriptors()
668 zynqmp_dma_free_desc_list(chan, &chan->done_list); in zynqmp_dma_free_descriptors()
669 spin_unlock_irqrestore(&chan->lock, irqflags); in zynqmp_dma_free_descriptors()
673 * zynqmp_dma_free_chan_resources - Free channel resources
681 dma_free_coherent(chan->dev, in zynqmp_dma_free_chan_resources()
683 chan->desc_pool_v, chan->desc_pool_p); in zynqmp_dma_free_chan_resources()
684 kfree(chan->sw_desc_pool); in zynqmp_dma_free_chan_resources()
685 pm_runtime_mark_last_busy(chan->dev); in zynqmp_dma_free_chan_resources()
686 pm_runtime_put_autosuspend(chan->dev); in zynqmp_dma_free_chan_resources()
690 * zynqmp_dma_reset - Reset the channel
691 * @chan: ZynqMP DMA channel pointer
697 writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS); in zynqmp_dma_reset()
699 spin_lock_irqsave(&chan->lock, irqflags); in zynqmp_dma_reset()
701 spin_unlock_irqrestore(&chan->lock, irqflags); in zynqmp_dma_reset()
709 * zynqmp_dma_irq_handler - ZynqMP DMA Interrupt handler
711 * @data: Pointer to the ZynqMP DMA channel structure
721 isr = readl(chan->regs + ZYNQMP_DMA_ISR); in zynqmp_dma_irq_handler()
722 imr = readl(chan->regs + ZYNQMP_DMA_IMR); in zynqmp_dma_irq_handler()
725 writel(isr, chan->regs + ZYNQMP_DMA_ISR); in zynqmp_dma_irq_handler()
727 tasklet_schedule(&chan->tasklet); in zynqmp_dma_irq_handler()
732 chan->idle = true; in zynqmp_dma_irq_handler()
735 chan->err = true; in zynqmp_dma_irq_handler()
736 tasklet_schedule(&chan->tasklet); in zynqmp_dma_irq_handler()
737 dev_err(chan->dev, "Channel %p has errors\n", chan); in zynqmp_dma_irq_handler()
743 dev_dbg(chan->dev, "Channel %p overflow interrupt\n", chan); in zynqmp_dma_irq_handler()
751 * zynqmp_dma_do_tasklet - Schedule completion tasklet
752 * @t: Pointer to the ZynqMP DMA channel structure
760 if (chan->err) { in zynqmp_dma_do_tasklet()
762 chan->err = false; in zynqmp_dma_do_tasklet()
766 spin_lock_irqsave(&chan->lock, irqflags); in zynqmp_dma_do_tasklet()
767 count = readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT); in zynqmp_dma_do_tasklet()
770 count--; in zynqmp_dma_do_tasklet()
772 spin_unlock_irqrestore(&chan->lock, irqflags); in zynqmp_dma_do_tasklet()
776 if (chan->idle) { in zynqmp_dma_do_tasklet()
777 spin_lock_irqsave(&chan->lock, irqflags); in zynqmp_dma_do_tasklet()
779 spin_unlock_irqrestore(&chan->lock, irqflags); in zynqmp_dma_do_tasklet()
784 * zynqmp_dma_device_terminate_all - Aborts all transfers on a channel
793 writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS); in zynqmp_dma_device_terminate_all()
800 * zynqmp_dma_synchronize - Synchronizes the termination of a transfers to the current context.
807 tasklet_kill(&chan->tasklet); in zynqmp_dma_synchronize()
811 * zynqmp_dma_prep_memcpy - prepare descriptors for memcpy transaction
835 spin_lock_irqsave(&chan->lock, irqflags); in zynqmp_dma_prep_memcpy()
836 if (desc_cnt > chan->desc_free_cnt) { in zynqmp_dma_prep_memcpy()
837 spin_unlock_irqrestore(&chan->lock, irqflags); in zynqmp_dma_prep_memcpy()
838 dev_dbg(chan->dev, "chan %p descs are not available\n", chan); in zynqmp_dma_prep_memcpy()
841 chan->desc_free_cnt = chan->desc_free_cnt - desc_cnt; in zynqmp_dma_prep_memcpy()
842 spin_unlock_irqrestore(&chan->lock, irqflags); in zynqmp_dma_prep_memcpy()
849 desc = (struct zynqmp_dma_desc_ll *)new->src_v; in zynqmp_dma_prep_memcpy()
853 len -= copy; in zynqmp_dma_prep_memcpy()
859 list_add_tail(&new->node, &first->tx_list); in zynqmp_dma_prep_memcpy()
863 async_tx_ack(&first->async_tx); in zynqmp_dma_prep_memcpy()
864 first->async_tx.flags = (enum dma_ctrl_flags)flags; in zynqmp_dma_prep_memcpy()
865 return &first->async_tx; in zynqmp_dma_prep_memcpy()
869 * zynqmp_dma_chan_remove - Channel remove function
870 * @chan: ZynqMP DMA channel pointer
877 if (chan->irq) in zynqmp_dma_chan_remove()
878 devm_free_irq(chan->zdev->dev, chan->irq, chan); in zynqmp_dma_chan_remove()
879 tasklet_kill(&chan->tasklet); in zynqmp_dma_chan_remove()
880 list_del(&chan->common.device_node); in zynqmp_dma_chan_remove()
884 * zynqmp_dma_chan_probe - Per Channel Probing
894 struct device_node *node = pdev->dev.of_node; in zynqmp_dma_chan_probe()
897 chan = devm_kzalloc(zdev->dev, sizeof(*chan), GFP_KERNEL); in zynqmp_dma_chan_probe()
899 return -ENOMEM; in zynqmp_dma_chan_probe()
900 chan->dev = zdev->dev; in zynqmp_dma_chan_probe()
901 chan->zdev = zdev; in zynqmp_dma_chan_probe()
903 chan->regs = devm_platform_ioremap_resource(pdev, 0); in zynqmp_dma_chan_probe()
904 if (IS_ERR(chan->regs)) in zynqmp_dma_chan_probe()
905 return PTR_ERR(chan->regs); in zynqmp_dma_chan_probe()
907 chan->bus_width = ZYNQMP_DMA_BUS_WIDTH_64; in zynqmp_dma_chan_probe()
908 chan->dst_burst_len = ZYNQMP_DMA_MAX_DST_BURST_LEN; in zynqmp_dma_chan_probe()
909 chan->src_burst_len = ZYNQMP_DMA_MAX_SRC_BURST_LEN; in zynqmp_dma_chan_probe()
910 err = of_property_read_u32(node, "xlnx,bus-width", &chan->bus_width); in zynqmp_dma_chan_probe()
912 dev_err(&pdev->dev, "missing xlnx,bus-width property\n"); in zynqmp_dma_chan_probe()
916 if (chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_64 && in zynqmp_dma_chan_probe()
917 chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_128) { in zynqmp_dma_chan_probe()
918 dev_err(zdev->dev, "invalid bus-width value"); in zynqmp_dma_chan_probe()
919 return -EINVAL; in zynqmp_dma_chan_probe()
922 chan->is_dmacoherent = of_property_read_bool(node, "dma-coherent"); in zynqmp_dma_chan_probe()
923 zdev->chan = chan; in zynqmp_dma_chan_probe()
924 tasklet_setup(&chan->tasklet, zynqmp_dma_do_tasklet); in zynqmp_dma_chan_probe()
925 spin_lock_init(&chan->lock); in zynqmp_dma_chan_probe()
926 INIT_LIST_HEAD(&chan->active_list); in zynqmp_dma_chan_probe()
927 INIT_LIST_HEAD(&chan->pending_list); in zynqmp_dma_chan_probe()
928 INIT_LIST_HEAD(&chan->done_list); in zynqmp_dma_chan_probe()
929 INIT_LIST_HEAD(&chan->free_list); in zynqmp_dma_chan_probe()
931 dma_cookie_init(&chan->common); in zynqmp_dma_chan_probe()
932 chan->common.device = &zdev->common; in zynqmp_dma_chan_probe()
933 list_add_tail(&chan->common.device_node, &zdev->common.channels); in zynqmp_dma_chan_probe()
936 chan->irq = platform_get_irq(pdev, 0); in zynqmp_dma_chan_probe()
937 if (chan->irq < 0) in zynqmp_dma_chan_probe()
938 return -ENXIO; in zynqmp_dma_chan_probe()
939 err = devm_request_irq(&pdev->dev, chan->irq, zynqmp_dma_irq_handler, 0, in zynqmp_dma_chan_probe()
940 "zynqmp-dma", chan); in zynqmp_dma_chan_probe()
944 chan->desc_size = sizeof(struct zynqmp_dma_desc_ll); in zynqmp_dma_chan_probe()
945 chan->idle = true; in zynqmp_dma_chan_probe()
950 * of_zynqmp_dma_xlate - Translation function
959 struct zynqmp_dma_device *zdev = ofdma->of_dma_data; in of_zynqmp_dma_xlate()
961 return dma_get_slave_channel(&zdev->chan->common); in of_zynqmp_dma_xlate()
965 * zynqmp_dma_suspend - Suspend method for the driver
980 * zynqmp_dma_resume - Resume from suspend
995 * zynqmp_dma_runtime_suspend - Runtime suspend method for the driver
1005 clk_disable_unprepare(zdev->clk_main); in zynqmp_dma_runtime_suspend()
1006 clk_disable_unprepare(zdev->clk_apb); in zynqmp_dma_runtime_suspend()
1012 * zynqmp_dma_runtime_resume - Runtime suspend method for the driver
1023 err = clk_prepare_enable(zdev->clk_main); in zynqmp_dma_runtime_resume()
1029 err = clk_prepare_enable(zdev->clk_apb); in zynqmp_dma_runtime_resume()
1032 clk_disable_unprepare(zdev->clk_main); in zynqmp_dma_runtime_resume()
1046 * zynqmp_dma_probe - Driver probe function
1057 zdev = devm_kzalloc(&pdev->dev, sizeof(*zdev), GFP_KERNEL); in zynqmp_dma_probe()
1059 return -ENOMEM; in zynqmp_dma_probe()
1061 zdev->dev = &pdev->dev; in zynqmp_dma_probe()
1062 INIT_LIST_HEAD(&zdev->common.channels); in zynqmp_dma_probe()
1064 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44)); in zynqmp_dma_probe()
1066 dev_err(&pdev->dev, "DMA not available for address range\n"); in zynqmp_dma_probe()
1069 dma_cap_set(DMA_MEMCPY, zdev->common.cap_mask); in zynqmp_dma_probe()
1071 p = &zdev->common; in zynqmp_dma_probe()
1072 p->device_prep_dma_memcpy = zynqmp_dma_prep_memcpy; in zynqmp_dma_probe()
1073 p->device_terminate_all = zynqmp_dma_device_terminate_all; in zynqmp_dma_probe()
1074 p->device_synchronize = zynqmp_dma_synchronize; in zynqmp_dma_probe()
1075 p->device_issue_pending = zynqmp_dma_issue_pending; in zynqmp_dma_probe()
1076 p->device_alloc_chan_resources = zynqmp_dma_alloc_chan_resources; in zynqmp_dma_probe()
1077 p->device_free_chan_resources = zynqmp_dma_free_chan_resources; in zynqmp_dma_probe()
1078 p->device_tx_status = dma_cookie_status; in zynqmp_dma_probe()
1079 p->device_config = zynqmp_dma_device_config; in zynqmp_dma_probe()
1080 p->dev = &pdev->dev; in zynqmp_dma_probe()
1082 zdev->clk_main = devm_clk_get(&pdev->dev, "clk_main"); in zynqmp_dma_probe()
1083 if (IS_ERR(zdev->clk_main)) in zynqmp_dma_probe()
1084 return dev_err_probe(&pdev->dev, PTR_ERR(zdev->clk_main), in zynqmp_dma_probe()
1087 zdev->clk_apb = devm_clk_get(&pdev->dev, "clk_apb"); in zynqmp_dma_probe()
1088 if (IS_ERR(zdev->clk_apb)) in zynqmp_dma_probe()
1089 return dev_err_probe(&pdev->dev, PTR_ERR(zdev->clk_apb), in zynqmp_dma_probe()
1093 pm_runtime_set_autosuspend_delay(zdev->dev, ZDMA_PM_TIMEOUT); in zynqmp_dma_probe()
1094 pm_runtime_use_autosuspend(zdev->dev); in zynqmp_dma_probe()
1095 pm_runtime_enable(zdev->dev); in zynqmp_dma_probe()
1096 ret = pm_runtime_resume_and_get(zdev->dev); in zynqmp_dma_probe()
1098 dev_err(&pdev->dev, "device wakeup failed.\n"); in zynqmp_dma_probe()
1099 pm_runtime_disable(zdev->dev); in zynqmp_dma_probe()
1101 if (!pm_runtime_enabled(zdev->dev)) { in zynqmp_dma_probe()
1102 ret = zynqmp_dma_runtime_resume(zdev->dev); in zynqmp_dma_probe()
1109 dev_err_probe(&pdev->dev, ret, "Probing channel failed\n"); in zynqmp_dma_probe()
1113 p->dst_addr_widths = BIT(zdev->chan->bus_width / 8); in zynqmp_dma_probe()
1114 p->src_addr_widths = BIT(zdev->chan->bus_width / 8); in zynqmp_dma_probe()
1116 ret = dma_async_device_register(&zdev->common); in zynqmp_dma_probe()
1118 dev_err(zdev->dev, "failed to register the dma device\n"); in zynqmp_dma_probe()
1122 ret = of_dma_controller_register(pdev->dev.of_node, in zynqmp_dma_probe()
1125 dev_err_probe(&pdev->dev, ret, "Unable to register DMA to DT\n"); in zynqmp_dma_probe()
1126 dma_async_device_unregister(&zdev->common); in zynqmp_dma_probe()
1130 pm_runtime_mark_last_busy(zdev->dev); in zynqmp_dma_probe()
1131 pm_runtime_put_sync_autosuspend(zdev->dev); in zynqmp_dma_probe()
1136 zynqmp_dma_chan_remove(zdev->chan); in zynqmp_dma_probe()
1138 if (!pm_runtime_enabled(zdev->dev)) in zynqmp_dma_probe()
1139 zynqmp_dma_runtime_suspend(zdev->dev); in zynqmp_dma_probe()
1140 pm_runtime_disable(zdev->dev); in zynqmp_dma_probe()
1145 * zynqmp_dma_remove - Driver remove function
1154 of_dma_controller_free(pdev->dev.of_node); in zynqmp_dma_remove()
1155 dma_async_device_unregister(&zdev->common); in zynqmp_dma_remove()
1157 zynqmp_dma_chan_remove(zdev->chan); in zynqmp_dma_remove()
1158 pm_runtime_disable(zdev->dev); in zynqmp_dma_remove()
1159 if (!pm_runtime_enabled(zdev->dev)) in zynqmp_dma_remove()
1160 zynqmp_dma_runtime_suspend(zdev->dev); in zynqmp_dma_remove()
1166 { .compatible = "xlnx,zynqmp-dma-1.0", },
1173 .name = "xilinx-zynqmp-dma",
1185 MODULE_DESCRIPTION("Xilinx ZynqMP DMA driver");