468 static inline u32 dpdma_read(void __iomem *base, u32 offset)  in dpdma_read()  function
480 	dpdma_write(base, offset, dpdma_read(base, offset) & ~clr);  in dpdma_clr()
485 	dpdma_write(base, offset, dpdma_read(base, offset) | set);  in dpdma_set()
906 			 dpdma_read(chan->reg, XILINX_DPDMA_CH_STATUS));  in xilinx_dpdma_chan_ostand()
1084 	desc_id = dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_ID)  in xilinx_dpdma_chan_vsync_irq()
1155 		dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE),  in xilinx_dpdma_chan_handle_err()
1156 		dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR));  in xilinx_dpdma_chan_handle_err()
1159 		dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDRE),  in xilinx_dpdma_chan_handle_err()
1160 		dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDR));  in xilinx_dpdma_chan_handle_err()
1517 	status = dpdma_read(xdev->reg, XILINX_DPDMA_ISR);  in xilinx_dpdma_irq_handler()
1518 	error = dpdma_read(xdev->reg, XILINX_DPDMA_EISR);  in xilinx_dpdma_irq_handler()