Lines Matching refs:XILINX_DMA_REG_DMASR

81 #define XILINX_DMA_REG_DMASR			0x0004  macro
1312 	return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,  in xilinx_dma_stop_transfer()
1327 	return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,  in xilinx_cdma_stop_transfer()
1344 	err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,  in xilinx_dma_start()
1350 			chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));  in xilinx_dma_start()
1762 			dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));  in xilinx_dma_reset()
1877 	status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR);  in xilinx_dma_irq_handler()
1881 	dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,  in xilinx_dma_irq_handler()
1894 		dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,  in xilinx_dma_irq_handler()
2490 				XILINX_DMA_REG_DMASR));  in xilinx_dma_terminate_all()
2931 		    dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) &  in xilinx_dma_chan_probe()