61 #define XILINX_DMA_REG_DMACR			0x0000  macro
1220 		dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,  in xilinx_dma_alloc_chan_resources()
1225 		dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,  in xilinx_dma_alloc_chan_resources()
1309 	dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);  in xilinx_dma_stop_transfer()
1341 	dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);  in xilinx_dma_start()
1390 	reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);  in xilinx_vdma_start_transfer()
1403 	dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);  in xilinx_vdma_start_transfer()
1466 	u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR);  in xilinx_cdma_start_transfer()
1488 		dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg);  in xilinx_cdma_start_transfer()
1492 		dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,  in xilinx_cdma_start_transfer()
1495 		dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,  in xilinx_cdma_start_transfer()
1556 	reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);  in xilinx_dma_start_transfer()
1562 		dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);  in xilinx_dma_start_transfer()
1570 	dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);  in xilinx_dma_start_transfer()
1752 	dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET);  in xilinx_dma_reset()
1755 	err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp,  in xilinx_dma_reset()
1761 			dma_ctrl_read(chan, XILINX_DMA_REG_DMACR),  in xilinx_dma_reset()
1790 	dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,  in xilinx_dma_chan_reset()
2353 	reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);  in xilinx_dma_prep_dma_cyclic()
2355 	dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);  in xilinx_dma_prep_dma_cyclic()
2502 		reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);  in xilinx_dma_terminate_all()
2504 		dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);  in xilinx_dma_terminate_all()
2509 		dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,  in xilinx_dma_terminate_all()
2544 	dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);  in xilinx_vdma_channel_set_config()
2587 	dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr);  in xilinx_vdma_channel_set_config()
2604 	dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,  in xilinx_dma_chan_remove()