90 	void __iomem *reg_ch_base;  member
170 	writel(val, xc->reg_ch_base + XDMAC_TFA);  in uniphier_xdmac_chan_start()
173 	writel(lower_32_bits(src_addr), xc->reg_ch_base + XDMAC_SAD);  in uniphier_xdmac_chan_start()
174 	writel(upper_32_bits(src_addr), xc->reg_ch_base + XDMAC_EXSAD);  in uniphier_xdmac_chan_start()
176 	writel(lower_32_bits(dst_addr), xc->reg_ch_base + XDMAC_DAD);  in uniphier_xdmac_chan_start()
177 	writel(upper_32_bits(dst_addr), xc->reg_ch_base + XDMAC_EXDAD);  in uniphier_xdmac_chan_start()
181 	writel(src_mode, xc->reg_ch_base + XDMAC_SADM);  in uniphier_xdmac_chan_start()
182 	writel(dst_mode, xc->reg_ch_base + XDMAC_DADM);  in uniphier_xdmac_chan_start()
184 	writel(its, xc->reg_ch_base + XDMAC_ITS);  in uniphier_xdmac_chan_start()
185 	writel(tnum, xc->reg_ch_base + XDMAC_TNUM);  in uniphier_xdmac_chan_start()
189 	       xc->reg_ch_base + XDMAC_IEN);  in uniphier_xdmac_chan_start()
192 	val = readl(xc->reg_ch_base + XDMAC_TSS);  in uniphier_xdmac_chan_start()
194 	writel(val, xc->reg_ch_base + XDMAC_TSS);  in uniphier_xdmac_chan_start()
203 	val = readl(xc->reg_ch_base + XDMAC_IEN);  in uniphier_xdmac_chan_stop()
205 	writel(val, xc->reg_ch_base + XDMAC_IEN);  in uniphier_xdmac_chan_stop()
208 	val = readl(xc->reg_ch_base + XDMAC_TSS);  in uniphier_xdmac_chan_stop()
210 	writel(0, xc->reg_ch_base + XDMAC_TSS);  in uniphier_xdmac_chan_stop()
213 	return readl_poll_timeout_atomic(xc->reg_ch_base + XDMAC_STAT, val,  in uniphier_xdmac_chan_stop()
237 	stat = readl(xc->reg_ch_base + XDMAC_ID);  in uniphier_xdmac_chan_irq()
259 	writel(stat, xc->reg_ch_base + XDMAC_IR);  in uniphier_xdmac_chan_irq()
460 	xc->reg_ch_base = xdev->reg_base + XDMAC_CH_WIDTH * ch;  in uniphier_xdmac_chan_init()