244 	evre_write_off = readl_relaxed(lldev->evca + HIDMA_EVCA_WRITE_PTR_REG);  in hidma_handle_tre_completion()
279 		    readl_relaxed(lldev->evca + HIDMA_EVCA_WRITE_PTR_REG);  in hidma_handle_tre_completion()
294 		writel(evre_read_off, lldev->evca + HIDMA_EVCA_DOORBELL_REG);  in hidma_handle_tre_completion()
334 	val = readl(lldev->evca + HIDMA_EVCA_CTRLSTS_REG);  in hidma_ll_reset()
337 	writel(val, lldev->evca + HIDMA_EVCA_CTRLSTS_REG);  in hidma_ll_reset()
343 	ret = readl_poll_timeout(lldev->evca + HIDMA_EVCA_CTRLSTS_REG, val,  in hidma_ll_reset()
395 		writel(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);  in hidma_ll_int_handler_internal()
408 	writel_relaxed(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);  in hidma_ll_int_handler_internal()
431 	status = readl_relaxed(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);  in hidma_ll_inthandler()
432 	enable = readl_relaxed(lldev->evca + HIDMA_EVCA_IRQ_EN_REG);  in hidma_ll_inthandler()
442 		status = readl_relaxed(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);  in hidma_ll_inthandler()
443 		enable = readl_relaxed(lldev->evca + HIDMA_EVCA_IRQ_EN_REG);  in hidma_ll_inthandler()
463 	val = readl(lldev->evca + HIDMA_EVCA_CTRLSTS_REG);  in hidma_ll_enable()
466 	writel(val, lldev->evca + HIDMA_EVCA_CTRLSTS_REG);  in hidma_ll_enable()
468 	ret = readl_poll_timeout(lldev->evca + HIDMA_EVCA_CTRLSTS_REG, val,  in hidma_ll_enable()
493 	writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);  in hidma_ll_enable()
513 	val = readl(lldev->evca + HIDMA_EVCA_CTRLSTS_REG);  in hidma_ll_isenabled()
575 	val = readl(lldev->evca + HIDMA_EVCA_CTRLSTS_REG);  in hidma_ll_disable()
578 	writel(val, lldev->evca + HIDMA_EVCA_CTRLSTS_REG);  in hidma_ll_disable()
584 	ret = readl_poll_timeout(lldev->evca + HIDMA_EVCA_CTRLSTS_REG, val,  in hidma_ll_disable()
594 	writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);  in hidma_ll_disable()
646 	writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);  in hidma_ll_setup()
649 	val = readl(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);  in hidma_ll_setup()
650 	writel(val, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);  in hidma_ll_setup()
660 	val = readl(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);  in hidma_ll_setup()
661 	writel(val, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);  in hidma_ll_setup()
664 	writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);  in hidma_ll_setup()
672 	writel(lower_32_bits(addr), lldev->evca + HIDMA_EVCA_RING_LOW_REG);  in hidma_ll_setup()
673 	writel(upper_32_bits(addr), lldev->evca + HIDMA_EVCA_RING_HIGH_REG);  in hidma_ll_setup()
675 			lldev->evca + HIDMA_EVCA_RING_LEN_REG);  in hidma_ll_setup()
694 	writel(0, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);  in hidma_ll_setup_irq()
695 	writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);  in hidma_ll_setup_irq()
698 	val = readl(lldev->evca + HIDMA_EVCA_INTCTRL_REG);  in hidma_ll_setup_irq()
702 	writel(val, lldev->evca + HIDMA_EVCA_INTCTRL_REG);  in hidma_ll_setup_irq()
705 	writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);  in hidma_ll_setup_irq()
706 	writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);  in hidma_ll_setup_irq()
710 				  void __iomem *trca, void __iomem *evca,  in hidma_ll_init()  argument
718 	if (!trca || !evca || !dev || !nr_tres)  in hidma_ll_init()
732 	lldev->evca = evca;  in hidma_ll_init()
797 	writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);  in hidma_ll_init()
828 	val = readl(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);  in hidma_ll_uninit()
829 	writel(val, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);  in hidma_ll_uninit()
830 	writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);  in hidma_ll_uninit()