dma/qcom/hidma.h

45 struct hidma_lldev {  struct
46 	bool msi_support;		/* flag indicating MSI support    */
47 	bool initialized;		/* initialized flag               */
48 	u8 trch_state;			/* trch_state of the device	  */
49 	u8 evch_state;			/* evch_state of the device	  */
50 	u8 chidx;			/* channel index in the core	  */
51 	u32 nr_tres;			/* max number of configs          */
52 	spinlock_t lock;		/* reentrancy                     */
53 	struct hidma_tre *trepool;	/* trepool of user configs */
54 	struct device *dev;		/* device			  */
55 	void __iomem *trca;		/* Transfer Channel address       */
56 	void __iomem *evca;		/* Event Channel address          */
58 		**pending_tre_list;	/* Pointers to pending TREs	  */
59 	atomic_t pending_tre_count;	/* Number of TREs pending	  */
61 	void *tre_ring;			/* TRE ring			  */
62 	dma_addr_t tre_dma;		/* TRE ring to be shared with HW  */
63 	u32 tre_ring_size;		/* Byte size of the ring	  */
64 	u32 tre_processed_off;		/* last processed TRE		  */
66 	void *evre_ring;		/* EVRE ring			   */
67 	dma_addr_t evre_dma;		/* EVRE ring to be shared with HW  */
68 	u32 evre_ring_size;		/* Byte size of the ring	   */
69 	u32 evre_processed_off;		/* last processed EVRE		   */
71 	u32 tre_write_offset;           /* TRE write location              */
72 	struct tasklet_struct task;	/* task delivering notifications   */