279 ldma_update_bits(struct ldma_dev *d, u32 mask, u32 val, u32 ofs)  in ldma_update_bits()  function
321 	ldma_update_bits(d, DMA_CTRL_RST, DMA_CTRL_RST, DMA_CTRL);  in ldma_dev_reset()
332 	ldma_update_bits(d, mask, val, DMA_CTRL);  in ldma_dev_pkt_arb_cfg()
343 	ldma_update_bits(d, mask, val, DMA_CTRL);  in ldma_dev_sram_desc_cfg()
359 	ldma_update_bits(d, mask, val, DMA_CTRL);  in ldma_dev_chan_flow_ctl_cfg()
372 	ldma_update_bits(d, mask, val, DMA_CPOLL);  in ldma_dev_global_polling_enable()
388 	ldma_update_bits(d, mask, val, DMA_CTRL);  in ldma_dev_desc_fetch_on_demand_cfg()
399 	ldma_update_bits(d, mask, val, DMA_CTRL);  in ldma_dev_byte_enable_cfg()
417 	ldma_update_bits(d, mask, val, DMA_ORRC);  in ldma_dev_orrc_cfg()
433 	ldma_update_bits(d, mask, val, DMA_CTRL);  in ldma_dev_df_tout_cfg()
449 	ldma_update_bits(d, mask, val, DMA_CTRL);  in ldma_dev_dburst_wr_cfg()
465 	ldma_update_bits(d, mask, val, DMA_CTRL);  in ldma_dev_vld_fetch_ack_cfg()
476 	ldma_update_bits(d, mask, val, DMA_CTRL);  in ldma_dev_drb_cfg()
527 	ldma_update_bits(d, DMA_CS_MASK, c->nr, DMA_CS);  in ldma_chan_cctrl_cfg()
565 	ldma_update_bits(d, DMA_CS_MASK, c->nr, DMA_CS);  in ldma_chan_irq_init()
571 	ldma_update_bits(d, cn_bit, 0, enofs);  in ldma_chan_irq_init()
589 	ldma_update_bits(d, DMA_CS_MASK, c->nr, DMA_CS);  in ldma_chan_set_class()
590 	ldma_update_bits(d, DMA_CCTRL_CLASS | DMA_CCTRL_CLASSH, class_val,  in ldma_chan_set_class()
604 	ldma_update_bits(d, DMA_CS_MASK, c->nr, DMA_CS);  in ldma_chan_on()
605 	ldma_update_bits(d, DMA_CCTRL_ON, DMA_CCTRL_ON, DMA_CCTRL);  in ldma_chan_on()
621 	ldma_update_bits(d, DMA_CS_MASK, c->nr, DMA_CS);  in ldma_chan_off()
622 	ldma_update_bits(d, DMA_CCTRL_ON, 0, DMA_CCTRL);  in ldma_chan_off()
642 	ldma_update_bits(d, DMA_CS_MASK, c->nr, DMA_CS);  in ldma_chan_desc_hw_cfg()
649 		ldma_update_bits(d, DMA_CDBA_MSB,  in ldma_chan_desc_hw_cfg()
706 	ldma_update_bits(d, DMA_CS_MASK, c->nr, DMA_CS);  in ldma_chan_reset()
707 	ldma_update_bits(d, DMA_CCTRL_RST, DMA_CCTRL_RST, DMA_CCTRL);  in ldma_chan_reset()
732 	ldma_update_bits(d, DMA_CS_MASK, c->nr, DMA_CS);  in ldma_chan_byte_offset_cfg()
733 	ldma_update_bits(d, mask, val, DMA_C_BOFF);  in ldma_chan_byte_offset_cfg()
748 	ldma_update_bits(d, DMA_CS_MASK, c->nr, DMA_CS);  in ldma_chan_data_endian_cfg()
749 	ldma_update_bits(d, mask, val, DMA_C_ENDIAN);  in ldma_chan_data_endian_cfg()
764 	ldma_update_bits(d, DMA_CS_MASK, c->nr, DMA_CS);  in ldma_chan_desc_endian_cfg()
765 	ldma_update_bits(d, mask, val, DMA_C_ENDIAN);  in ldma_chan_desc_endian_cfg()
783 	ldma_update_bits(d, DMA_CS_MASK, c->nr, DMA_CS);  in ldma_chan_hdr_mode_cfg()
784 	ldma_update_bits(d, mask, val, DMA_C_HDRM);  in ldma_chan_hdr_mode_cfg()
799 	ldma_update_bits(d, DMA_CS_MASK, c->nr, DMA_CS);  in ldma_chan_rxwr_np_cfg()
800 	ldma_update_bits(d, mask, val, DMA_CCTRL);  in ldma_chan_rxwr_np_cfg()
814 	ldma_update_bits(d, DMA_CS_MASK, c->nr, DMA_CS);  in ldma_chan_abc_cfg()
815 	ldma_update_bits(d, mask, val, DMA_CCTRL);  in ldma_chan_abc_cfg()