Lines Matching +full:imx25 +full:- +full:uart
1 // SPDX-License-Identifier: GPL-2.0+
3 // drivers/dma/imx-sdma.c
11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
27 #include <linux/dma-mapping.h>
38 #include <linux/dma/imx-dma.h>
41 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
44 #include "virt-dma.h"
129 * 0-7 Lower WML Lower watermark level
140 * 13-15 --------- MUST BE 0
141 * 16-23 Higher WML HWML
142 * 24-27 N Total number of samples after
153 * 30 --------- MUST BE 0
193 * struct sdma_script_start_addrs - SDMA script start pointers
252 * Mode/Count of data node descriptors - IPCv2
271 * struct sdma_channel_control - Channel control Block
285 * struct sdma_state_registers - SDMA context for a channel
314 * struct sdma_context_data - sdma context specific to a channel
372 * struct sdma_desc - descriptor structor for one transfer
379 * @chn_real_count: the real count updated from bd->mode.count
398 * struct sdma_channel - housekeeping for a SDMA channel
479 * struct sdma_firmware_header - Layout of the firmware image
667 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
668 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
669 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
670 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
671 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
672 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
673 { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
674 { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, },
675 { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
681 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
687 u32 chnenbl0 = sdma->drvdata->chnenbl0; in chnenbl_ofs()
694 struct sdma_engine *sdma = sdmac->sdma; in sdma_config_ownership()
695 int channel = sdmac->channel; in sdma_config_ownership()
699 return -EINVAL; in sdma_config_ownership()
701 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); in sdma_config_ownership()
702 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); in sdma_config_ownership()
703 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); in sdma_config_ownership()
720 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); in sdma_config_ownership()
721 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); in sdma_config_ownership()
722 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); in sdma_config_ownership()
729 return !!(readl(sdma->regs + SDMA_H_STATSTOP) & BIT(channel)); in is_sdma_channel_enabled()
734 writel(BIT(channel), sdma->regs + SDMA_H_START); in sdma_enable_channel()
738 * sdma_run_channel0 - run a channel and wait till it's done
747 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP, in sdma_run_channel0()
750 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); in sdma_run_channel0()
753 reg = readl(sdma->regs + SDMA_H_CONFIG); in sdma_run_channel0()
756 writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG); in sdma_run_channel0()
765 struct sdma_buffer_descriptor *bd0 = sdma->bd0; in sdma_load_script()
771 buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL); in sdma_load_script()
773 return -ENOMEM; in sdma_load_script()
775 spin_lock_irqsave(&sdma->channel_0_lock, flags); in sdma_load_script()
777 bd0->mode.command = C0_SETPM; in sdma_load_script()
778 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; in sdma_load_script()
779 bd0->mode.count = size / 2; in sdma_load_script()
780 bd0->buffer_addr = buf_phys; in sdma_load_script()
781 bd0->ext_buffer_addr = address; in sdma_load_script()
787 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); in sdma_load_script()
789 dma_free_coherent(sdma->dev, size, buf_virt, buf_phys); in sdma_load_script()
796 struct sdma_engine *sdma = sdmac->sdma; in sdma_event_enable()
797 int channel = sdmac->channel; in sdma_event_enable()
801 val = readl_relaxed(sdma->regs + chnenbl); in sdma_event_enable()
803 writel_relaxed(val, sdma->regs + chnenbl); in sdma_event_enable()
806 if (sdmac->sw_done) { in sdma_event_enable()
807 val = readl_relaxed(sdma->regs + SDMA_DONE0_CONFIG); in sdma_event_enable()
810 writel_relaxed(val, sdma->regs + SDMA_DONE0_CONFIG); in sdma_event_enable()
816 struct sdma_engine *sdma = sdmac->sdma; in sdma_event_disable()
817 int channel = sdmac->channel; in sdma_event_disable()
821 val = readl_relaxed(sdma->regs + chnenbl); in sdma_event_disable()
823 writel_relaxed(val, sdma->regs + chnenbl); in sdma_event_disable()
833 struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc); in sdma_start_desc()
835 struct sdma_engine *sdma = sdmac->sdma; in sdma_start_desc()
836 int channel = sdmac->channel; in sdma_start_desc()
839 sdmac->desc = NULL; in sdma_start_desc()
842 sdmac->desc = desc = to_sdma_desc(&vd->tx); in sdma_start_desc()
844 list_del(&vd->node); in sdma_start_desc()
846 sdma->channel_control[channel].base_bd_ptr = desc->bd_phys; in sdma_start_desc()
847 sdma->channel_control[channel].current_bd_ptr = desc->bd_phys; in sdma_start_desc()
848 sdma_enable_channel(sdma, sdmac->channel); in sdma_start_desc()
855 enum dma_status old_status = sdmac->status; in sdma_update_channel_loop()
858 * loop mode. Iterate over descriptors, re-setup them and in sdma_update_channel_loop()
861 while (sdmac->desc) { in sdma_update_channel_loop()
862 struct sdma_desc *desc = sdmac->desc; in sdma_update_channel_loop()
864 bd = &desc->bd[desc->buf_tail]; in sdma_update_channel_loop()
866 if (bd->mode.status & BD_DONE) in sdma_update_channel_loop()
869 if (bd->mode.status & BD_RROR) { in sdma_update_channel_loop()
870 bd->mode.status &= ~BD_RROR; in sdma_update_channel_loop()
871 sdmac->status = DMA_ERROR; in sdma_update_channel_loop()
872 error = -EIO; in sdma_update_channel_loop()
876 * We use bd->mode.count to calculate the residue, since contains in sdma_update_channel_loop()
880 desc->chn_real_count = bd->mode.count; in sdma_update_channel_loop()
881 bd->mode.count = desc->period_len; in sdma_update_channel_loop()
882 desc->buf_ptail = desc->buf_tail; in sdma_update_channel_loop()
883 desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd; in sdma_update_channel_loop()
891 spin_unlock(&sdmac->vc.lock); in sdma_update_channel_loop()
892 dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL); in sdma_update_channel_loop()
893 spin_lock(&sdmac->vc.lock); in sdma_update_channel_loop()
896 bd->mode.status |= BD_DONE; in sdma_update_channel_loop()
899 sdmac->status = old_status; in sdma_update_channel_loop()
906 if (sdmac->desc && !is_sdma_channel_enabled(sdmac->sdma, sdmac->channel)) { in sdma_update_channel_loop()
907 dev_warn(sdmac->sdma->dev, "restart cyclic channel %d\n", sdmac->channel); in sdma_update_channel_loop()
908 sdma_enable_channel(sdmac->sdma, sdmac->channel); in sdma_update_channel_loop()
918 sdmac->desc->chn_real_count = 0; in mxc_sdma_handle_channel_normal()
923 for (i = 0; i < sdmac->desc->num_bd; i++) { in mxc_sdma_handle_channel_normal()
924 bd = &sdmac->desc->bd[i]; in mxc_sdma_handle_channel_normal()
926 if (bd->mode.status & (BD_DONE | BD_RROR)) in mxc_sdma_handle_channel_normal()
927 error = -EIO; in mxc_sdma_handle_channel_normal()
928 sdmac->desc->chn_real_count += bd->mode.count; in mxc_sdma_handle_channel_normal()
932 sdmac->status = DMA_ERROR; in mxc_sdma_handle_channel_normal()
934 sdmac->status = DMA_COMPLETE; in mxc_sdma_handle_channel_normal()
942 stat = readl_relaxed(sdma->regs + SDMA_H_INTR); in sdma_int_handler()
943 writel_relaxed(stat, sdma->regs + SDMA_H_INTR); in sdma_int_handler()
948 int channel = fls(stat) - 1; in sdma_int_handler()
949 struct sdma_channel *sdmac = &sdma->channel[channel]; in sdma_int_handler()
952 spin_lock(&sdmac->vc.lock); in sdma_int_handler()
953 desc = sdmac->desc; in sdma_int_handler()
955 if (sdmac->flags & IMX_DMA_SG_LOOP) { in sdma_int_handler()
956 if (sdmac->peripheral_type != IMX_DMATYPE_HDMI) in sdma_int_handler()
959 vchan_cyclic_callback(&desc->vd); in sdma_int_handler()
962 vchan_cookie_complete(&desc->vd); in sdma_int_handler()
967 spin_unlock(&sdmac->vc.lock); in sdma_int_handler()
980 struct sdma_engine *sdma = sdmac->sdma; in sdma_get_pc()
984 * two peripherals or memory-to-memory transfers in sdma_get_pc()
988 sdmac->pc_from_device = 0; in sdma_get_pc()
989 sdmac->pc_to_device = 0; in sdma_get_pc()
990 sdmac->device_to_device = 0; in sdma_get_pc()
991 sdmac->pc_to_pc = 0; in sdma_get_pc()
992 sdmac->is_ram_script = false; in sdma_get_pc()
996 emi_2_emi = sdma->script_addrs->ap_2_ap_addr; in sdma_get_pc()
999 emi_2_per = sdma->script_addrs->bp_2_ap_addr; in sdma_get_pc()
1000 per_2_emi = sdma->script_addrs->ap_2_bp_addr; in sdma_get_pc()
1003 per_2_emi = sdma->script_addrs->firi_2_mcu_addr; in sdma_get_pc()
1004 emi_2_per = sdma->script_addrs->mcu_2_firi_addr; in sdma_get_pc()
1007 per_2_emi = sdma->script_addrs->uart_2_mcu_addr; in sdma_get_pc()
1008 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
1011 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; in sdma_get_pc()
1012 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
1015 per_2_emi = sdma->script_addrs->ata_2_mcu_addr; in sdma_get_pc()
1016 emi_2_per = sdma->script_addrs->mcu_2_ata_addr; in sdma_get_pc()
1019 per_2_emi = sdma->script_addrs->app_2_mcu_addr; in sdma_get_pc()
1022 if (sdmac->sdma->drvdata->ecspi_fixed) { in sdma_get_pc()
1023 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
1025 emi_2_per = sdma->script_addrs->mcu_2_ecspi_addr; in sdma_get_pc()
1026 sdmac->is_ram_script = true; in sdma_get_pc()
1033 per_2_emi = sdma->script_addrs->app_2_mcu_addr; in sdma_get_pc()
1034 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
1037 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; in sdma_get_pc()
1038 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; in sdma_get_pc()
1039 sdmac->is_ram_script = true; in sdma_get_pc()
1047 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; in sdma_get_pc()
1048 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
1051 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; in sdma_get_pc()
1052 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; in sdma_get_pc()
1053 per_2_per = sdma->script_addrs->per_2_per_addr; in sdma_get_pc()
1054 sdmac->is_ram_script = true; in sdma_get_pc()
1057 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; in sdma_get_pc()
1058 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
1059 per_2_per = sdma->script_addrs->per_2_per_addr; in sdma_get_pc()
1062 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; in sdma_get_pc()
1063 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; in sdma_get_pc()
1066 per_2_emi = sdma->script_addrs->dptc_dvfs_addr; in sdma_get_pc()
1069 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; in sdma_get_pc()
1070 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; in sdma_get_pc()
1073 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; in sdma_get_pc()
1076 per_2_emi = sdma->script_addrs->sai_2_mcu_addr; in sdma_get_pc()
1077 emi_2_per = sdma->script_addrs->mcu_2_sai_addr; in sdma_get_pc()
1080 emi_2_per = sdma->script_addrs->hdmi_dma_addr; in sdma_get_pc()
1081 sdmac->is_ram_script = true; in sdma_get_pc()
1084 dev_err(sdma->dev, "Unsupported transfer type %d\n", in sdma_get_pc()
1086 return -EINVAL; in sdma_get_pc()
1089 sdmac->pc_from_device = per_2_emi; in sdma_get_pc()
1090 sdmac->pc_to_device = emi_2_per; in sdma_get_pc()
1091 sdmac->device_to_device = per_2_per; in sdma_get_pc()
1092 sdmac->pc_to_pc = emi_2_emi; in sdma_get_pc()
1099 struct sdma_engine *sdma = sdmac->sdma; in sdma_load_context()
1100 int channel = sdmac->channel; in sdma_load_context()
1102 struct sdma_context_data *context = sdma->context; in sdma_load_context()
1103 struct sdma_buffer_descriptor *bd0 = sdma->bd0; in sdma_load_context()
1107 if (sdmac->direction == DMA_DEV_TO_MEM) in sdma_load_context()
1108 load_address = sdmac->pc_from_device; in sdma_load_context()
1109 else if (sdmac->direction == DMA_DEV_TO_DEV) in sdma_load_context()
1110 load_address = sdmac->device_to_device; in sdma_load_context()
1111 else if (sdmac->direction == DMA_MEM_TO_MEM) in sdma_load_context()
1112 load_address = sdmac->pc_to_pc; in sdma_load_context()
1114 load_address = sdmac->pc_to_device; in sdma_load_context()
1119 dev_dbg(sdma->dev, "load_address = %d\n", load_address); in sdma_load_context()
1120 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); in sdma_load_context()
1121 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); in sdma_load_context()
1122 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); in sdma_load_context()
1123 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); in sdma_load_context()
1124 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); in sdma_load_context()
1126 spin_lock_irqsave(&sdma->channel_0_lock, flags); in sdma_load_context()
1129 context->channel_state.pc = load_address; in sdma_load_context()
1134 if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) { in sdma_load_context()
1135 context->gReg[4] = sdmac->per_addr; in sdma_load_context()
1136 context->gReg[6] = sdmac->shp_addr; in sdma_load_context()
1138 context->gReg[0] = sdmac->event_mask[1]; in sdma_load_context()
1139 context->gReg[1] = sdmac->event_mask[0]; in sdma_load_context()
1140 context->gReg[2] = sdmac->per_addr; in sdma_load_context()
1141 context->gReg[6] = sdmac->shp_addr; in sdma_load_context()
1142 context->gReg[7] = sdmac->watermark_level; in sdma_load_context()
1145 bd0->mode.command = C0_SETDM; in sdma_load_context()
1146 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; in sdma_load_context()
1147 bd0->mode.count = sizeof(*context) / 4; in sdma_load_context()
1148 bd0->buffer_addr = sdma->context_phys; in sdma_load_context()
1149 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; in sdma_load_context()
1152 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); in sdma_load_context()
1165 struct sdma_engine *sdma = sdmac->sdma; in sdma_disable_channel()
1166 int channel = sdmac->channel; in sdma_disable_channel()
1168 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); in sdma_disable_channel()
1169 sdmac->status = DMA_ERROR; in sdma_disable_channel()
1185 vchan_dma_desc_free_list(&sdmac->vc, &sdmac->terminated); in sdma_channel_terminate_work()
1193 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_terminate_all()
1197 if (sdmac->desc) { in sdma_terminate_all()
1198 vchan_terminate_vdesc(&sdmac->desc->vd); in sdma_terminate_all()
1205 vchan_get_all_descriptors(&sdmac->vc, &sdmac->terminated); in sdma_terminate_all()
1206 sdmac->desc = NULL; in sdma_terminate_all()
1207 schedule_work(&sdmac->terminate_worker); in sdma_terminate_all()
1210 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_terminate_all()
1219 vchan_synchronize(&sdmac->vc); in sdma_channel_synchronize()
1221 flush_work(&sdmac->terminate_worker); in sdma_channel_synchronize()
1226 struct sdma_engine *sdma = sdmac->sdma; in sdma_set_watermarklevel_for_p2p()
1228 int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML; in sdma_set_watermarklevel_for_p2p()
1229 int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16; in sdma_set_watermarklevel_for_p2p()
1231 set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]); in sdma_set_watermarklevel_for_p2p()
1232 set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]); in sdma_set_watermarklevel_for_p2p()
1234 if (sdmac->event_id0 > 31) in sdma_set_watermarklevel_for_p2p()
1235 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE; in sdma_set_watermarklevel_for_p2p()
1237 if (sdmac->event_id1 > 31) in sdma_set_watermarklevel_for_p2p()
1238 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE; in sdma_set_watermarklevel_for_p2p()
1246 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML | in sdma_set_watermarklevel_for_p2p()
1248 sdmac->watermark_level |= hwml; in sdma_set_watermarklevel_for_p2p()
1249 sdmac->watermark_level |= lwml << 16; in sdma_set_watermarklevel_for_p2p()
1250 swap(sdmac->event_mask[0], sdmac->event_mask[1]); in sdma_set_watermarklevel_for_p2p()
1253 if (sdmac->per_address2 >= sdma->spba_start_addr && in sdma_set_watermarklevel_for_p2p()
1254 sdmac->per_address2 <= sdma->spba_end_addr) in sdma_set_watermarklevel_for_p2p()
1255 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP; in sdma_set_watermarklevel_for_p2p()
1257 if (sdmac->per_address >= sdma->spba_start_addr && in sdma_set_watermarklevel_for_p2p()
1258 sdmac->per_address <= sdma->spba_end_addr) in sdma_set_watermarklevel_for_p2p()
1259 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP; in sdma_set_watermarklevel_for_p2p()
1261 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT; in sdma_set_watermarklevel_for_p2p()
1270 if (sdmac->sw_done) in sdma_set_watermarklevel_for_sais()
1271 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SW_DONE; in sdma_set_watermarklevel_for_sais()
1273 if (sdmac->direction == DMA_DEV_TO_MEM) { in sdma_set_watermarklevel_for_sais()
1274 n_fifos = sdmac->n_fifos_src; in sdma_set_watermarklevel_for_sais()
1275 stride_fifos = sdmac->stride_fifos_src; in sdma_set_watermarklevel_for_sais()
1277 n_fifos = sdmac->n_fifos_dst; in sdma_set_watermarklevel_for_sais()
1278 stride_fifos = sdmac->stride_fifos_dst; in sdma_set_watermarklevel_for_sais()
1281 words_per_fifo = sdmac->words_per_fifo; in sdma_set_watermarklevel_for_sais()
1283 sdmac->watermark_level |= in sdma_set_watermarklevel_for_sais()
1285 sdmac->watermark_level |= in sdma_set_watermarklevel_for_sais()
1288 sdmac->watermark_level |= in sdma_set_watermarklevel_for_sais()
1289 FIELD_PREP(SDMA_WATERMARK_LEVEL_WORDS_PER_FIFO, (words_per_fifo - 1)); in sdma_set_watermarklevel_for_sais()
1299 sdmac->event_mask[0] = 0; in sdma_config_channel()
1300 sdmac->event_mask[1] = 0; in sdma_config_channel()
1301 sdmac->shp_addr = 0; in sdma_config_channel()
1302 sdmac->per_addr = 0; in sdma_config_channel()
1304 switch (sdmac->peripheral_type) { in sdma_config_channel()
1316 ret = sdma_get_pc(sdmac, sdmac->peripheral_type); in sdma_config_channel()
1320 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && in sdma_config_channel()
1321 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { in sdma_config_channel()
1323 if (sdmac->event_id1) { in sdma_config_channel()
1324 if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP || in sdma_config_channel()
1325 sdmac->peripheral_type == IMX_DMATYPE_ASRC) in sdma_config_channel()
1328 if (sdmac->peripheral_type == in sdma_config_channel()
1332 __set_bit(sdmac->event_id0, sdmac->event_mask); in sdma_config_channel()
1336 sdmac->shp_addr = sdmac->per_address; in sdma_config_channel()
1337 sdmac->per_addr = sdmac->per_address2; in sdma_config_channel()
1339 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ in sdma_config_channel()
1348 struct sdma_engine *sdma = sdmac->sdma; in sdma_set_channel_priority()
1349 int channel = sdmac->channel; in sdma_set_channel_priority()
1353 return -EINVAL; in sdma_set_channel_priority()
1356 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); in sdma_set_channel_priority()
1363 int ret = -EBUSY; in sdma_request_channel0()
1365 sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys, in sdma_request_channel0()
1367 if (!sdma->bd0) { in sdma_request_channel0()
1368 ret = -ENOMEM; in sdma_request_channel0()
1372 sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys; in sdma_request_channel0()
1373 sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys; in sdma_request_channel0()
1375 sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY); in sdma_request_channel0()
1385 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); in sdma_alloc_bd()
1388 desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size, in sdma_alloc_bd()
1389 &desc->bd_phys, GFP_NOWAIT); in sdma_alloc_bd()
1390 if (!desc->bd) { in sdma_alloc_bd()
1391 ret = -ENOMEM; in sdma_alloc_bd()
1400 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); in sdma_free_bd()
1402 dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd, in sdma_free_bd()
1403 desc->bd_phys); in sdma_free_bd()
1417 struct imx_dma_data *data = chan->private; in sdma_alloc_chan_resources()
1422 * MEMCPY may never setup chan->private by filter function such as in sdma_alloc_chan_resources()
1424 * Please note in any other slave case, you have to setup chan->private in sdma_alloc_chan_resources()
1431 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n"); in sdma_alloc_chan_resources()
1443 switch (data->priority) { in sdma_alloc_chan_resources()
1456 sdmac->peripheral_type = data->peripheral_type; in sdma_alloc_chan_resources()
1457 sdmac->event_id0 = data->dma_request; in sdma_alloc_chan_resources()
1458 sdmac->event_id1 = data->dma_request2; in sdma_alloc_chan_resources()
1460 ret = clk_enable(sdmac->sdma->clk_ipg); in sdma_alloc_chan_resources()
1463 ret = clk_enable(sdmac->sdma->clk_ahb); in sdma_alloc_chan_resources()
1474 clk_disable(sdmac->sdma->clk_ahb); in sdma_alloc_chan_resources()
1476 clk_disable(sdmac->sdma->clk_ipg); in sdma_alloc_chan_resources()
1483 struct sdma_engine *sdma = sdmac->sdma; in sdma_free_chan_resources()
1489 sdma_event_disable(sdmac, sdmac->event_id0); in sdma_free_chan_resources()
1490 if (sdmac->event_id1) in sdma_free_chan_resources()
1491 sdma_event_disable(sdmac, sdmac->event_id1); in sdma_free_chan_resources()
1493 sdmac->event_id0 = 0; in sdma_free_chan_resources()
1494 sdmac->event_id1 = 0; in sdma_free_chan_resources()
1498 clk_disable(sdma->clk_ipg); in sdma_free_chan_resources()
1499 clk_disable(sdma->clk_ahb); in sdma_free_chan_resources()
1507 if (!sdmac->sdma->fw_loaded && sdmac->is_ram_script) { in sdma_transfer_init()
1508 dev_warn_once(sdmac->sdma->dev, "sdma firmware not ready!\n"); in sdma_transfer_init()
1516 sdmac->status = DMA_IN_PROGRESS; in sdma_transfer_init()
1517 sdmac->direction = direction; in sdma_transfer_init()
1518 sdmac->flags = 0; in sdma_transfer_init()
1520 desc->chn_count = 0; in sdma_transfer_init()
1521 desc->chn_real_count = 0; in sdma_transfer_init()
1522 desc->buf_tail = 0; in sdma_transfer_init()
1523 desc->buf_ptail = 0; in sdma_transfer_init()
1524 desc->sdmac = sdmac; in sdma_transfer_init()
1525 desc->num_bd = bds; in sdma_transfer_init()
1552 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_memcpy()
1553 int channel = sdmac->channel; in sdma_prep_memcpy()
1562 dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n", in sdma_prep_memcpy()
1572 bd = &desc->bd[i]; in sdma_prep_memcpy()
1573 bd->buffer_addr = dma_src; in sdma_prep_memcpy()
1574 bd->ext_buffer_addr = dma_dst; in sdma_prep_memcpy()
1575 bd->mode.count = count; in sdma_prep_memcpy()
1576 desc->chn_count += count; in sdma_prep_memcpy()
1577 bd->mode.command = 0; in sdma_prep_memcpy()
1581 len -= count; in sdma_prep_memcpy()
1592 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n", in sdma_prep_memcpy()
1593 i, count, bd->buffer_addr, in sdma_prep_memcpy()
1597 bd->mode.status = param; in sdma_prep_memcpy()
1600 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_memcpy()
1609 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_slave_sg()
1611 int channel = sdmac->channel; in sdma_prep_slave_sg()
1615 sdma_config_write(chan, &sdmac->slave_config, direction); in sdma_prep_slave_sg()
1621 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", in sdma_prep_slave_sg()
1625 struct sdma_buffer_descriptor *bd = &desc->bd[i]; in sdma_prep_slave_sg()
1628 bd->buffer_addr = sg->dma_address; in sdma_prep_slave_sg()
1633 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", in sdma_prep_slave_sg()
1638 bd->mode.count = count; in sdma_prep_slave_sg()
1639 desc->chn_count += count; in sdma_prep_slave_sg()
1641 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) in sdma_prep_slave_sg()
1644 switch (sdmac->word_size) { in sdma_prep_slave_sg()
1646 bd->mode.command = 0; in sdma_prep_slave_sg()
1647 if (count & 3 || sg->dma_address & 3) in sdma_prep_slave_sg()
1651 bd->mode.command = 2; in sdma_prep_slave_sg()
1652 if (count & 1 || sg->dma_address & 1) in sdma_prep_slave_sg()
1656 bd->mode.command = 1; in sdma_prep_slave_sg()
1670 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", in sdma_prep_slave_sg()
1671 i, count, (u64)sg->dma_address, in sdma_prep_slave_sg()
1675 bd->mode.status = param; in sdma_prep_slave_sg()
1678 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_slave_sg()
1683 sdmac->status = DMA_ERROR; in sdma_prep_slave_sg()
1693 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_dma_cyclic()
1695 int channel = sdmac->channel; in sdma_prep_dma_cyclic()
1699 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); in sdma_prep_dma_cyclic()
1701 if (sdmac->peripheral_type != IMX_DMATYPE_HDMI) in sdma_prep_dma_cyclic()
1704 sdma_config_write(chan, &sdmac->slave_config, direction); in sdma_prep_dma_cyclic()
1710 desc->period_len = period_len; in sdma_prep_dma_cyclic()
1712 sdmac->flags |= IMX_DMA_SG_LOOP; in sdma_prep_dma_cyclic()
1715 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n", in sdma_prep_dma_cyclic()
1720 if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) in sdma_prep_dma_cyclic()
1721 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_dma_cyclic()
1724 struct sdma_buffer_descriptor *bd = &desc->bd[i]; in sdma_prep_dma_cyclic()
1727 bd->buffer_addr = dma_addr; in sdma_prep_dma_cyclic()
1729 bd->mode.count = period_len; in sdma_prep_dma_cyclic()
1731 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) in sdma_prep_dma_cyclic()
1733 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) in sdma_prep_dma_cyclic()
1734 bd->mode.command = 0; in sdma_prep_dma_cyclic()
1736 bd->mode.command = sdmac->word_size; in sdma_prep_dma_cyclic()
1742 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n", in sdma_prep_dma_cyclic()
1747 bd->mode.status = param; in sdma_prep_dma_cyclic()
1755 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_dma_cyclic()
1760 sdmac->status = DMA_ERROR; in sdma_prep_dma_cyclic()
1771 sdmac->per_address = dmaengine_cfg->src_addr; in sdma_config_write()
1772 sdmac->watermark_level = dmaengine_cfg->src_maxburst * in sdma_config_write()
1773 dmaengine_cfg->src_addr_width; in sdma_config_write()
1774 sdmac->word_size = dmaengine_cfg->src_addr_width; in sdma_config_write()
1776 sdmac->per_address2 = dmaengine_cfg->src_addr; in sdma_config_write()
1777 sdmac->per_address = dmaengine_cfg->dst_addr; in sdma_config_write()
1778 sdmac->watermark_level = dmaengine_cfg->src_maxburst & in sdma_config_write()
1780 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) & in sdma_config_write()
1782 sdmac->word_size = dmaengine_cfg->dst_addr_width; in sdma_config_write()
1783 } else if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) { in sdma_config_write()
1784 sdmac->per_address = dmaengine_cfg->dst_addr; in sdma_config_write()
1785 sdmac->per_address2 = dmaengine_cfg->src_addr; in sdma_config_write()
1786 sdmac->watermark_level = 0; in sdma_config_write()
1788 sdmac->per_address = dmaengine_cfg->dst_addr; in sdma_config_write()
1789 sdmac->watermark_level = dmaengine_cfg->dst_maxburst * in sdma_config_write()
1790 dmaengine_cfg->dst_addr_width; in sdma_config_write()
1791 sdmac->word_size = dmaengine_cfg->dst_addr_width; in sdma_config_write()
1793 sdmac->direction = direction; in sdma_config_write()
1801 struct sdma_engine *sdma = sdmac->sdma; in sdma_config()
1803 memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg)); in sdma_config()
1805 if (dmaengine_cfg->peripheral_config) { in sdma_config()
1806 struct sdma_peripheral_config *sdmacfg = dmaengine_cfg->peripheral_config; in sdma_config()
1807 if (dmaengine_cfg->peripheral_size != sizeof(struct sdma_peripheral_config)) { in sdma_config()
1808 dev_err(sdma->dev, "Invalid peripheral size %zu, expected %zu\n", in sdma_config()
1809 dmaengine_cfg->peripheral_size, in sdma_config()
1811 return -EINVAL; in sdma_config()
1813 sdmac->n_fifos_src = sdmacfg->n_fifos_src; in sdma_config()
1814 sdmac->n_fifos_dst = sdmacfg->n_fifos_dst; in sdma_config()
1815 sdmac->stride_fifos_src = sdmacfg->stride_fifos_src; in sdma_config()
1816 sdmac->stride_fifos_dst = sdmacfg->stride_fifos_dst; in sdma_config()
1817 sdmac->words_per_fifo = sdmacfg->words_per_fifo; in sdma_config()
1818 sdmac->sw_done = sdmacfg->sw_done; in sdma_config()
1822 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) in sdma_config()
1823 return -EINVAL; in sdma_config()
1824 sdma_event_enable(sdmac, sdmac->event_id0); in sdma_config()
1826 if (sdmac->event_id1) { in sdma_config()
1827 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) in sdma_config()
1828 return -EINVAL; in sdma_config()
1829 sdma_event_enable(sdmac, sdmac->event_id1); in sdma_config()
1850 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_tx_status()
1852 vd = vchan_find_desc(&sdmac->vc, cookie); in sdma_tx_status()
1854 desc = to_sdma_desc(&vd->tx); in sdma_tx_status()
1855 else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie) in sdma_tx_status()
1856 desc = sdmac->desc; in sdma_tx_status()
1859 if (sdmac->flags & IMX_DMA_SG_LOOP) in sdma_tx_status()
1860 residue = (desc->num_bd - desc->buf_ptail) * in sdma_tx_status()
1861 desc->period_len - desc->chn_real_count; in sdma_tx_status()
1863 residue = desc->chn_count - desc->chn_real_count; in sdma_tx_status()
1868 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_tx_status()
1870 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, in sdma_tx_status()
1873 return sdmac->status; in sdma_tx_status()
1881 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_issue_pending()
1882 if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc) in sdma_issue_pending()
1884 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_issue_pending()
1896 s32 *saddr_arr = (u32 *)sdma->script_addrs; in sdma_add_scripts()
1900 if (!sdma->script_number) in sdma_add_scripts()
1901 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; in sdma_add_scripts()
1903 if (sdma->script_number > sizeof(struct sdma_script_start_addrs) in sdma_add_scripts()
1905 dev_err(sdma->dev, in sdma_add_scripts()
1907 sdma->script_number); in sdma_add_scripts()
1911 for (i = 0; i < sdma->script_number; i++) in sdma_add_scripts()
1917 * is based on uart ram script and mainline kernel based on uart rom in sdma_add_scripts()
1918 * script, both uart ram/rom scripts are present in newer sdma in sdma_add_scripts()
1921 if (sdma->script_number >= SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3) { in sdma_add_scripts()
1922 if (addr->uart_2_mcu_rom_addr) in sdma_add_scripts()
1923 sdma->script_addrs->uart_2_mcu_addr = addr->uart_2_mcu_rom_addr; in sdma_add_scripts()
1924 if (addr->uartsh_2_mcu_rom_addr) in sdma_add_scripts()
1925 sdma->script_addrs->uartsh_2_mcu_addr = addr->uartsh_2_mcu_rom_addr; in sdma_add_scripts()
1937 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); in sdma_load_firmware()
1942 if (fw->size < sizeof(*header)) in sdma_load_firmware()
1945 header = (struct sdma_firmware_header *)fw->data; in sdma_load_firmware()
1947 if (header->magic != SDMA_FIRMWARE_MAGIC) in sdma_load_firmware()
1949 if (header->ram_code_start + header->ram_code_size > fw->size) in sdma_load_firmware()
1951 switch (header->version_major) { in sdma_load_firmware()
1953 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; in sdma_load_firmware()
1956 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; in sdma_load_firmware()
1959 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3; in sdma_load_firmware()
1962 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4; in sdma_load_firmware()
1965 dev_err(sdma->dev, "unknown firmware version\n"); in sdma_load_firmware()
1969 addr = (void *)header + header->script_addrs_start; in sdma_load_firmware()
1970 ram_code = (void *)header + header->ram_code_start; in sdma_load_firmware()
1972 clk_enable(sdma->clk_ipg); in sdma_load_firmware()
1973 clk_enable(sdma->clk_ahb); in sdma_load_firmware()
1976 header->ram_code_size, in sdma_load_firmware()
1977 addr->ram_code_start_addr); in sdma_load_firmware()
1978 clk_disable(sdma->clk_ipg); in sdma_load_firmware()
1979 clk_disable(sdma->clk_ahb); in sdma_load_firmware()
1983 sdma->fw_loaded = true; in sdma_load_firmware()
1985 dev_info(sdma->dev, "loaded firmware %d.%d\n", in sdma_load_firmware()
1986 header->version_major, in sdma_load_firmware()
1987 header->version_minor); in sdma_load_firmware()
1997 struct device_node *np = sdma->dev->of_node; in sdma_event_remap()
2001 char propname[] = "fsl,sdma-event-remap"; in sdma_event_remap()
2009 num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0; in sdma_event_remap()
2011 dev_dbg(sdma->dev, "no event needs to be remapped\n"); in sdma_event_remap()
2014 dev_err(sdma->dev, "the property %s must modulo %d\n", in sdma_event_remap()
2016 ret = -EINVAL; in sdma_event_remap()
2022 dev_err(sdma->dev, "failed to get gpr regmap\n"); in sdma_event_remap()
2030 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
2037 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
2044 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
2065 FW_ACTION_UEVENT, fw_name, sdma->dev, in sdma_get_firmware()
2076 ret = clk_enable(sdma->clk_ipg); in sdma_init()
2079 ret = clk_enable(sdma->clk_ahb); in sdma_init()
2083 if (sdma->drvdata->check_ratio && in sdma_init()
2084 (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg))) in sdma_init()
2085 sdma->clk_ratio = 1; in sdma_init()
2088 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); in sdma_init()
2090 sdma->channel_control = dma_alloc_coherent(sdma->dev, in sdma_init()
2095 if (!sdma->channel_control) { in sdma_init()
2096 ret = -ENOMEM; in sdma_init()
2100 sdma->context = (void *)sdma->channel_control + in sdma_init()
2102 sdma->context_phys = ccb_phys + in sdma_init()
2106 for (i = 0; i < sdma->drvdata->num_events; i++) in sdma_init()
2107 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); in sdma_init()
2111 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); in sdma_init()
2117 sdma_config_ownership(&sdma->channel[0], false, true, false); in sdma_init()
2120 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); in sdma_init()
2123 if (sdma->clk_ratio) in sdma_init()
2124 writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG); in sdma_init()
2126 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); in sdma_init()
2128 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); in sdma_init()
2131 sdma_set_channel_priority(&sdma->channel[0], 7); in sdma_init()
2133 clk_disable(sdma->clk_ipg); in sdma_init()
2134 clk_disable(sdma->clk_ahb); in sdma_init()
2139 clk_disable(sdma->clk_ahb); in sdma_init()
2141 clk_disable(sdma->clk_ipg); in sdma_init()
2142 dev_err(sdma->dev, "initialisation failed with %d\n", ret); in sdma_init()
2154 sdmac->data = *data; in sdma_filter_fn()
2155 chan->private = &sdmac->data; in sdma_filter_fn()
2163 struct sdma_engine *sdma = ofdma->of_dma_data; in sdma_xlate()
2164 dma_cap_mask_t mask = sdma->dma_device.cap_mask; in sdma_xlate()
2167 if (dma_spec->args_count != 3) in sdma_xlate()
2170 data.dma_request = dma_spec->args[0]; in sdma_xlate()
2171 data.peripheral_type = dma_spec->args[1]; in sdma_xlate()
2172 data.priority = dma_spec->args[2]; in sdma_xlate()
2176 * chan->private will point to the imx_dma_data, and in in sdma_xlate()
2178 * be set to sdmac->event_id1. in sdma_xlate()
2183 ofdma->of_node); in sdma_xlate()
2188 struct device_node *np = pdev->dev.of_node; in sdma_probe()
2198 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in sdma_probe()
2202 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL); in sdma_probe()
2204 return -ENOMEM; in sdma_probe()
2206 spin_lock_init(&sdma->channel_0_lock); in sdma_probe()
2208 sdma->dev = &pdev->dev; in sdma_probe()
2209 sdma->drvdata = of_device_get_match_data(sdma->dev); in sdma_probe()
2215 sdma->regs = devm_platform_ioremap_resource(pdev, 0); in sdma_probe()
2216 if (IS_ERR(sdma->regs)) in sdma_probe()
2217 return PTR_ERR(sdma->regs); in sdma_probe()
2219 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in sdma_probe()
2220 if (IS_ERR(sdma->clk_ipg)) in sdma_probe()
2221 return PTR_ERR(sdma->clk_ipg); in sdma_probe()
2223 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); in sdma_probe()
2224 if (IS_ERR(sdma->clk_ahb)) in sdma_probe()
2225 return PTR_ERR(sdma->clk_ahb); in sdma_probe()
2227 ret = clk_prepare(sdma->clk_ipg); in sdma_probe()
2231 ret = clk_prepare(sdma->clk_ahb); in sdma_probe()
2235 ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, in sdma_probe()
2236 dev_name(&pdev->dev), sdma); in sdma_probe()
2240 sdma->irq = irq; in sdma_probe()
2242 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); in sdma_probe()
2243 if (!sdma->script_addrs) { in sdma_probe()
2244 ret = -ENOMEM; in sdma_probe()
2249 saddr_arr = (s32 *)sdma->script_addrs; in sdma_probe()
2250 for (i = 0; i < sizeof(*sdma->script_addrs) / sizeof(s32); i++) in sdma_probe()
2251 saddr_arr[i] = -EINVAL; in sdma_probe()
2253 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); in sdma_probe()
2254 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); in sdma_probe()
2255 dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask); in sdma_probe()
2256 dma_cap_set(DMA_PRIVATE, sdma->dma_device.cap_mask); in sdma_probe()
2258 INIT_LIST_HEAD(&sdma->dma_device.channels); in sdma_probe()
2261 struct sdma_channel *sdmac = &sdma->channel[i]; in sdma_probe()
2263 sdmac->sdma = sdma; in sdma_probe()
2265 sdmac->channel = i; in sdma_probe()
2266 sdmac->vc.desc_free = sdma_desc_free; in sdma_probe()
2267 INIT_LIST_HEAD(&sdmac->terminated); in sdma_probe()
2268 INIT_WORK(&sdmac->terminate_worker, in sdma_probe()
2276 vchan_init(&sdmac->vc, &sdma->dma_device); in sdma_probe()
2287 if (sdma->drvdata->script_addrs) in sdma_probe()
2288 sdma_add_scripts(sdma, sdma->drvdata->script_addrs); in sdma_probe()
2290 sdma->dma_device.dev = &pdev->dev; in sdma_probe()
2292 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; in sdma_probe()
2293 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; in sdma_probe()
2294 sdma->dma_device.device_tx_status = sdma_tx_status; in sdma_probe()
2295 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; in sdma_probe()
2296 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; in sdma_probe()
2297 sdma->dma_device.device_config = sdma_config; in sdma_probe()
2298 sdma->dma_device.device_terminate_all = sdma_terminate_all; in sdma_probe()
2299 sdma->dma_device.device_synchronize = sdma_channel_synchronize; in sdma_probe()
2300 sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS; in sdma_probe()
2301 sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS; in sdma_probe()
2302 sdma->dma_device.directions = SDMA_DMA_DIRECTIONS; in sdma_probe()
2303 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; in sdma_probe()
2304 sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy; in sdma_probe()
2305 sdma->dma_device.device_issue_pending = sdma_issue_pending; in sdma_probe()
2306 sdma->dma_device.copy_align = 2; in sdma_probe()
2307 dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT); in sdma_probe()
2311 ret = dma_async_device_register(&sdma->dma_device); in sdma_probe()
2313 dev_err(&pdev->dev, "unable to register\n"); in sdma_probe()
2320 dev_err(&pdev->dev, "failed to register controller\n"); in sdma_probe()
2324 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus"); in sdma_probe()
2327 sdma->spba_start_addr = spba_res.start; in sdma_probe()
2328 sdma->spba_end_addr = spba_res.end; in sdma_probe()
2338 ret = of_property_read_string(np, "fsl,sdma-ram-script-name", in sdma_probe()
2341 dev_warn(&pdev->dev, "failed to get firmware name\n"); in sdma_probe()
2345 dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); in sdma_probe()
2351 dma_async_device_unregister(&sdma->dma_device); in sdma_probe()
2353 kfree(sdma->script_addrs); in sdma_probe()
2355 clk_unprepare(sdma->clk_ahb); in sdma_probe()
2357 clk_unprepare(sdma->clk_ipg); in sdma_probe()
2366 devm_free_irq(&pdev->dev, sdma->irq, sdma); in sdma_remove()
2367 dma_async_device_unregister(&sdma->dma_device); in sdma_remove()
2368 kfree(sdma->script_addrs); in sdma_remove()
2369 clk_unprepare(sdma->clk_ahb); in sdma_remove()
2370 clk_unprepare(sdma->clk_ipg); in sdma_remove()
2373 struct sdma_channel *sdmac = &sdma->channel[i]; in sdma_remove()
2375 tasklet_kill(&sdmac->vc.task); in sdma_remove()
2376 sdma_free_chan_resources(&sdmac->vc.chan); in sdma_remove()
2385 .name = "imx-sdma",
2397 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
2400 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");