Lines Matching +full:0 +full:- +full:job +full:- +full:ring
13 * Copyright (c) 2010-2012 Freescale Semiconductor, Inc.
47 #define FSL_RE_GFM_POLY 0x1d000000
50 #define FSL_RE_CFG1_CBSI 0x08000000
51 #define FSL_RE_CFG1_CBS0 0x00080000
56 #define FSL_RE_PQ_OPCODE 0x1B
57 #define FSL_RE_XOR_OPCODE 0x1A
58 #define FSL_RE_MOVE_OPCODE 0x8
60 #define FSL_RE_BLOCK_SIZE 0x3 /* 4096 bytes */
61 #define FSL_RE_CACHEABLE_IO 0x0
62 #define FSL_RE_BUFFER_OUTPUT 0x0
63 #define FSL_RE_INTR_ON_ERROR 0x1
64 #define FSL_RE_DATA_DEP 0x1
65 #define FSL_RE_ENABLE_DPI 0x0
66 #define FSL_RE_RING_SIZE 0x400
67 #define FSL_RE_RING_SIZE_MASK (FSL_RE_RING_SIZE - 1)
70 #define FSL_RE_ADDR_BIT_MASK (BIT(FSL_RE_ADDR_BIT_SHIFT) - 1)
71 #define FSL_RE_ERROR 0x40000000
72 #define FSL_RE_INTR 0x80000000
73 #define FSL_RE_CLR_INTR 0x80000000
74 #define FSL_RE_PAUSE 0x80000000
75 #define FSL_RE_ENABLE 0x80000000
76 #define FSL_RE_REG_LIODN_MASK 0x00000FFF
78 #define FSL_RE_CDB_OPCODE_MASK 0xF8000000
80 #define FSL_RE_CDB_EXCLEN_MASK 0x03000000
82 #define FSL_RE_CDB_EXCLQ1_MASK 0x00F00000
84 #define FSL_RE_CDB_EXCLQ2_MASK 0x000F0000
86 #define FSL_RE_CDB_BLKSIZE_MASK 0x0000C000
88 #define FSL_RE_CDB_CACHE_MASK 0x00003000
90 #define FSL_RE_CDB_BUFFER_MASK 0x00000800
92 #define FSL_RE_CDB_ERROR_MASK 0x00000400
94 #define FSL_RE_CDB_NRCS_MASK 0x0000003C
96 #define FSL_RE_CDB_DEPEND_MASK 0x00000008
98 #define FSL_RE_CDB_DPI_MASK 0x00000004
135 __be32 jr_config_0; /* Job Queue Configuration 0 Register */
136 __be32 jr_config_1; /* Job Queue Configuration 1 Register */
137 __be32 jr_interrupt_status; /* Job Queue Interrupt Status Register */
139 __be32 jr_command; /* Job Queue Command Register */
141 __be32 jr_status; /* Job Queue Status Register */
144 /* Input Ring */
145 __be32 inbring_base_h; /* Inbound Ring Base Address Register - High */
146 __be32 inbring_base_l; /* Inbound Ring Base Address Register - Low */
147 __be32 inbring_size; /* Inbound Ring Size Register */
149 __be32 inbring_slot_avail; /* Inbound Ring Slot Available Register */
151 __be32 inbring_add_job; /* Inbound Ring Add Job Register */
153 __be32 inbring_cnsmr_indx; /* Inbound Ring Consumer Index Register */
156 /* Output Ring */
157 __be32 oubring_base_h; /* Outbound Ring Base Address Register - High */
158 __be32 oubring_base_l; /* Outbound Ring Base Address Register - Low */
159 __be32 oubring_size; /* Outbound Ring Size Register */
161 __be32 oubring_job_rmvd; /* Outbound Ring Job Removed Register */
163 __be32 oubring_slot_full; /* Outbound Ring Slot Full Register */
165 __be32 oubring_prdcr_indx; /* Outbound Ring Producer Index */
177 #define FSL_RE_DPI_APPS_MASK 0xC0000000
179 #define FSL_RE_DPI_REF_MASK 0x30000000
181 #define FSL_RE_DPI_GUARD_MASK 0x0C000000
183 #define FSL_RE_DPI_ATTR_MASK 0x03000000
185 #define FSL_RE_DPI_META_MASK 0x0000FFFF
203 /* CDB for no-op command */
221 #define FSL_RE_CF_ADDR_HIGH_MASK 0x000000FF
222 #define FSL_RE_CF_EXT_MASK 0x80000000
224 #define FSL_RE_CF_FINAL_MASK 0x40000000
226 #define FSL_RE_CF_LENGTH_MASK 0x000FFFFF
227 #define FSL_RE_CF_BPID_MASK 0x00FF0000
229 #define FSL_RE_CF_OFFSET_MASK 0x00001FFF
239 #define FSL_RE_HWDESC_LIODN_MASK 0x3F000000
241 #define FSL_RE_HWDESC_BPID_MASK 0x00FF0000
243 #define FSL_RE_HWDESC_ELIODN_MASK 0x0000F000
246 #define FSL_RE_HWDESC_FMT_MASK (0x3 << FSL_RE_HWDESC_FMT_SHIFT)
265 /* Per job ring data structure */
281 /* hw descriptor ring for inbound queue*/
286 /* hw descriptor ring for outbound queue */