Lines Matching full:dw
32 #include "dw-axi-dmac.h"
37 * The set of bus widths supported by the DMA controller. DW AXI DMAC supports
94 if (chan->chip->dw->hdata->reg_map_8_channels && in axi_chan_config_write()
95 !chan->chip->dw->hdata->use_cfg2) { in axi_chan_config_write()
189 if (chan->chip->dw->hdata->reg_map_8_channels) in axi_chan_disable()
201 if (chan->chip->dw->hdata->reg_map_8_channels) in axi_chan_enable()
224 for (i = 0; i < chip->dw->hdata->nr_channels; i++) { in axi_dma_hw_init()
225 axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL); in axi_dma_hw_init()
226 axi_chan_disable(&chip->dw->chan[i]); in axi_dma_hw_init()
236 u32 max_width = chan->chip->dw->hdata->m_data_width; in axi_chan_get_xfer_width()
380 u32 priority = chan->chip->dw->hdata->priority[chan->id]; in axi_chan_block_xfer_start()
595 if (desc->chan->chip->dw->hdata->nr_masters > 1) in set_desc_dest_master()
607 unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width); in dw_axi_dma_set_hw_desc()
616 axi_block_ts = chan->chip->dw->hdata->block_size[chan->id]; in dw_axi_dma_set_hw_desc()
659 if (chan->chip->dw->hdata->restrict_axi_burst_len) { in dw_axi_dma_set_hw_desc()
660 burst_len = chan->chip->dw->hdata->axi_rw_burst_len; in dw_axi_dma_set_hw_desc()
695 axi_block_ts = chan->chip->dw->hdata->block_size[chan->id]; in calculate_block_len()
699 data_width = BIT(chan->chip->dw->hdata->m_data_width); in calculate_block_len()
889 max_block_ts = chan->chip->dw->hdata->block_size[chan->id]; in dma_chan_prep_dma_memcpy()
930 if (chan->chip->dw->hdata->restrict_axi_burst_len) { in dma_chan_prep_dma_memcpy()
931 u32 burst_len = chan->chip->dw->hdata->axi_rw_burst_len; in dma_chan_prep_dma_memcpy()
1106 struct dw_axi_dma *dw = chip->dw; in dw_axi_dma_interrupt() local
1115 for (i = 0; i < dw->hdata->nr_channels; i++) { in dw_axi_dma_interrupt()
1116 chan = &dw->chan[i]; in dw_axi_dma_interrupt()
1180 if (chan->chip->dw->hdata->reg_map_8_channels) { in dma_chan_pause()
1213 if (chan->chip->dw->hdata->reg_map_8_channels) { in axi_chan_resume()
1289 struct dw_axi_dma *dw = ofdma->of_dma_data; in dw_axi_dma_of_xlate() local
1293 dchan = dma_get_any_slave_channel(&dw->dma); in dw_axi_dma_of_xlate()
1314 chip->dw->hdata->nr_channels = tmp; in parse_device_properties()
1316 chip->dw->hdata->reg_map_8_channels = true; in parse_device_properties()
1324 chip->dw->hdata->nr_masters = tmp; in parse_device_properties()
1332 chip->dw->hdata->m_data_width = tmp; in parse_device_properties()
1335 chip->dw->hdata->nr_channels); in parse_device_properties()
1338 for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) { in parse_device_properties()
1342 chip->dw->hdata->block_size[tmp] = carr[tmp]; in parse_device_properties()
1346 chip->dw->hdata->nr_channels); in parse_device_properties()
1350 for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) { in parse_device_properties()
1351 if (carr[tmp] >= chip->dw->hdata->nr_channels) in parse_device_properties()
1354 chip->dw->hdata->priority[tmp] = carr[tmp]; in parse_device_properties()
1365 chip->dw->hdata->restrict_axi_burst_len = true; in parse_device_properties()
1366 chip->dw->hdata->axi_rw_burst_len = tmp; in parse_device_properties()
1375 struct dw_axi_dma *dw; in dw_probe() local
1386 dw = devm_kzalloc(&pdev->dev, sizeof(*dw), GFP_KERNEL); in dw_probe()
1387 if (!dw) in dw_probe()
1394 chip->dw = dw; in dw_probe()
1396 chip->dw->hdata = hdata; in dw_probe()
1423 chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2); in dw_probe()
1437 dw->chan = devm_kcalloc(chip->dev, hdata->nr_channels, in dw_probe()
1438 sizeof(*dw->chan), GFP_KERNEL); in dw_probe()
1439 if (!dw->chan) in dw_probe()
1447 INIT_LIST_HEAD(&dw->dma.channels); in dw_probe()
1449 struct axi_dma_chan *chan = &dw->chan[i]; in dw_probe()
1457 vchan_init(&chan->vc, &dw->dma); in dw_probe()
1461 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); in dw_probe()
1462 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); in dw_probe()
1463 dma_cap_set(DMA_CYCLIC, dw->dma.cap_mask); in dw_probe()
1466 dw->dma.max_burst = hdata->axi_rw_burst_len; in dw_probe()
1467 dw->dma.src_addr_widths = AXI_DMA_BUSWIDTHS; in dw_probe()
1468 dw->dma.dst_addr_widths = AXI_DMA_BUSWIDTHS; in dw_probe()
1469 dw->dma.directions = BIT(DMA_MEM_TO_MEM); in dw_probe()
1470 dw->dma.directions |= BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); in dw_probe()
1471 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; in dw_probe()
1473 dw->dma.dev = chip->dev; in dw_probe()
1474 dw->dma.device_tx_status = dma_chan_tx_status; in dw_probe()
1475 dw->dma.device_issue_pending = dma_chan_issue_pending; in dw_probe()
1476 dw->dma.device_terminate_all = dma_chan_terminate_all; in dw_probe()
1477 dw->dma.device_pause = dma_chan_pause; in dw_probe()
1478 dw->dma.device_resume = dma_chan_resume; in dw_probe()
1480 dw->dma.device_alloc_chan_resources = dma_chan_alloc_chan_resources; in dw_probe()
1481 dw->dma.device_free_chan_resources = dma_chan_free_chan_resources; in dw_probe()
1483 dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy; in dw_probe()
1484 dw->dma.device_synchronize = dw_axi_dma_synchronize; in dw_probe()
1485 dw->dma.device_config = dw_axi_dma_chan_slave_config; in dw_probe()
1486 dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg; in dw_probe()
1487 dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic; in dw_probe()
1494 dw->dma.dev->dma_parms = &dw->dma_parms; in dw_probe()
1514 ret = dmaenginem_async_device_register(&dw->dma); in dw_probe()
1520 dw_axi_dma_of_xlate, dw); in dw_probe()
1526 dw->hdata->nr_channels); in dw_probe()
1539 struct dw_axi_dma *dw = chip->dw; in dw_remove() local
1547 for (i = 0; i < dw->hdata->nr_channels; i++) { in dw_remove()
1548 axi_chan_disable(&chip->dw->chan[i]); in dw_remove()
1549 axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL); in dw_remove()
1560 list_for_each_entry_safe(chan, _chan, &dw->dma.channels, in dw_remove()