1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Ingenic JZ4780 DMA controller
6  * Author: Alex Smith <alex@alex-smith.me.uk>
11 #include <linux/dma-mapping.h>
21 #include "virt-dma.h"
37 /* Per-channel registers. */
98  * struct jz4780_dma_hwdesc - descriptor structure read by the DMA controller.
179 	return container_of(jzchan->vchan.chan.device, struct jz4780_dma_dev,  in jz4780_dma_chan_parent()
186 	return readl(jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn));  in jz4780_dma_chn_readl()
192 	writel(val, jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn));  in jz4780_dma_chn_writel()
198 	return readl(jzdma->ctrl_base + reg);  in jz4780_dma_ctrl_readl()
204 	writel(val, jzdma->ctrl_base + reg);  in jz4780_dma_ctrl_writel()
210 	if (jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) {  in jz4780_dma_chan_enable()
213 		if (jzdma->soc_data->flags & JZ_SOC_DATA_NO_DCKES_DCKEC)  in jz4780_dma_chan_enable()
225 	if ((jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) &&  in jz4780_dma_chan_disable()
226 			!(jzdma->soc_data->flags & JZ_SOC_DATA_NO_DCKES_DCKEC))  in jz4780_dma_chan_disable()
244 	desc->desc = dma_pool_alloc(jzchan->desc_pool, GFP_NOWAIT,  in jz4780_dma_desc_alloc()
245 				    &desc->desc_phys);  in jz4780_dma_desc_alloc()
246 	if (!desc->desc) {  in jz4780_dma_desc_alloc()
251 	desc->count = count;  in jz4780_dma_desc_alloc()
252 	desc->type = type;  in jz4780_dma_desc_alloc()
255 		desc->transfer_type = jzchan->transfer_type_rx;  in jz4780_dma_desc_alloc()
257 		desc->transfer_type = jzchan->transfer_type_tx;  in jz4780_dma_desc_alloc()
265 	struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(vdesc->tx.chan);  in jz4780_dma_desc_free()
267 	dma_pool_free(jzchan->desc_pool, desc->desc, desc->desc_phys);  in jz4780_dma_desc_free()
275 	int ord = ffs(val) - 1;  in jz4780_dma_transfer_size()
286 	else if (ord > jzdma->soc_data->transfer_ord_max)  in jz4780_dma_transfer_size()
287 		ord = jzdma->soc_data->transfer_ord_max;  in jz4780_dma_transfer_size()
313 	struct dma_slave_config *config = &jzchan->config;  in jz4780_dma_setup_hwdesc()
317 		desc->dcm = JZ_DMA_DCM_SAI;  in jz4780_dma_setup_hwdesc()
318 		desc->dsa = addr;  in jz4780_dma_setup_hwdesc()
319 		desc->dta = config->dst_addr;  in jz4780_dma_setup_hwdesc()
321 		width = config->dst_addr_width;  in jz4780_dma_setup_hwdesc()
322 		maxburst = config->dst_maxburst;  in jz4780_dma_setup_hwdesc()
324 		desc->dcm = JZ_DMA_DCM_DAI;  in jz4780_dma_setup_hwdesc()
325 		desc->dsa = config->src_addr;  in jz4780_dma_setup_hwdesc()
326 		desc->dta = addr;  in jz4780_dma_setup_hwdesc()
328 		width = config->src_addr_width;  in jz4780_dma_setup_hwdesc()
329 		maxburst = config->src_maxburst;  in jz4780_dma_setup_hwdesc()
340 				       &jzchan->transfer_shift);  in jz4780_dma_setup_hwdesc()
350 		return -EINVAL;  in jz4780_dma_setup_hwdesc()
353 	desc->dcm |= tsz << JZ_DMA_DCM_TSZ_SHIFT;  in jz4780_dma_setup_hwdesc()
354 	desc->dcm |= width << JZ_DMA_DCM_SP_SHIFT;  in jz4780_dma_setup_hwdesc()
355 	desc->dcm |= width << JZ_DMA_DCM_DP_SHIFT;  in jz4780_dma_setup_hwdesc()
357 	desc->dtc = len >> jzchan->transfer_shift;  in jz4780_dma_setup_hwdesc()
377 		err = jz4780_dma_setup_hwdesc(jzchan, &desc->desc[i],  in jz4780_dma_prep_slave_sg()
382 			jz4780_dma_desc_free(&jzchan->desc->vdesc);  in jz4780_dma_prep_slave_sg()
386 		desc->desc[i].dcm |= JZ_DMA_DCM_TIE;  in jz4780_dma_prep_slave_sg()
388 		if (i != (sg_len - 1) &&  in jz4780_dma_prep_slave_sg()
389 		    !(jzdma->soc_data->flags & JZ_SOC_DATA_BREAK_LINKS)) {  in jz4780_dma_prep_slave_sg()
391 			desc->desc[i].dcm |= JZ_DMA_DCM_LINK;  in jz4780_dma_prep_slave_sg()
398 			desc->desc[i].dtc |=  in jz4780_dma_prep_slave_sg()
399 				(((i + 1) * sizeof(*desc->desc)) >> 4) << 24;  in jz4780_dma_prep_slave_sg()
403 	return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags);  in jz4780_dma_prep_slave_sg()
426 		err = jz4780_dma_setup_hwdesc(jzchan, &desc->desc[i], buf_addr,  in jz4780_dma_prep_dma_cyclic()
429 			jz4780_dma_desc_free(&jzchan->desc->vdesc);  in jz4780_dma_prep_dma_cyclic()
441 		desc->desc[i].dcm |= JZ_DMA_DCM_TIE | JZ_DMA_DCM_LINK;  in jz4780_dma_prep_dma_cyclic()
449 		if (i != (periods - 1)) {  in jz4780_dma_prep_dma_cyclic()
450 			desc->desc[i].dtc |=  in jz4780_dma_prep_dma_cyclic()
451 				(((i + 1) * sizeof(*desc->desc)) >> 4) << 24;  in jz4780_dma_prep_dma_cyclic()
455 	return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags);  in jz4780_dma_prep_dma_cyclic()
471 				       &jzchan->transfer_shift);  in jz4780_dma_prep_dma_memcpy()
473 	desc->transfer_type = JZ_DMA_DRT_AUTO;  in jz4780_dma_prep_dma_memcpy()
475 	desc->desc[0].dsa = src;  in jz4780_dma_prep_dma_memcpy()
476 	desc->desc[0].dta = dest;  in jz4780_dma_prep_dma_memcpy()
477 	desc->desc[0].dcm = JZ_DMA_DCM_TIE | JZ_DMA_DCM_SAI | JZ_DMA_DCM_DAI |  in jz4780_dma_prep_dma_memcpy()
481 	desc->desc[0].dtc = len >> jzchan->transfer_shift;  in jz4780_dma_prep_dma_memcpy()
483 	return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags);  in jz4780_dma_prep_dma_memcpy()
493 	if (!jzchan->desc) {  in jz4780_dma_begin()
494 		vdesc = vchan_next_desc(&jzchan->vchan);  in jz4780_dma_begin()
498 		list_del(&vdesc->node);  in jz4780_dma_begin()
500 		jzchan->desc = to_jz4780_dma_desc(vdesc);  in jz4780_dma_begin()
501 		jzchan->curr_hwdesc = 0;  in jz4780_dma_begin()
503 		if (jzchan->desc->type == DMA_CYCLIC && vdesc->tx.callback) {  in jz4780_dma_begin()
505 			 * The DMA controller doesn't support triggering an  in jz4780_dma_begin()
508 			 * descriptors. For a cyclic DMA setup the list of  in jz4780_dma_begin()
512 			 * If the user requested a callback for a cyclic DMA  in jz4780_dma_begin()
518 			for (i = 0; i < jzchan->desc->count; i++)  in jz4780_dma_begin()
519 				jzchan->desc->desc[i].dcm &= ~JZ_DMA_DCM_LINK;  in jz4780_dma_begin()
527 		jzchan->curr_hwdesc =  in jz4780_dma_begin()
528 			(jzchan->curr_hwdesc + 1) % jzchan->desc->count;  in jz4780_dma_begin()
532 	jz4780_dma_chan_enable(jzdma, jzchan->id);  in jz4780_dma_begin()
534 	/* Use 4-word descriptors. */  in jz4780_dma_begin()
535 	jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0);  in jz4780_dma_begin()
538 	jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DRT,  in jz4780_dma_begin()
539 			      jzchan->desc->transfer_type);  in jz4780_dma_begin()
542 	 * Set the transfer count. This is redundant for a descriptor-driven  in jz4780_dma_begin()
547 	jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DTC,  in jz4780_dma_begin()
548 				jzchan->desc->desc[jzchan->curr_hwdesc].dtc);  in jz4780_dma_begin()
551 	desc_phys = jzchan->desc->desc_phys +  in jz4780_dma_begin()
552 		    (jzchan->curr_hwdesc * sizeof(*jzchan->desc->desc));  in jz4780_dma_begin()
553 	jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DDA, desc_phys);  in jz4780_dma_begin()
554 	jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DDRS, BIT(jzchan->id));  in jz4780_dma_begin()
557 	jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS,  in jz4780_dma_begin()
566 	spin_lock_irqsave(&jzchan->vchan.lock, flags);  in jz4780_dma_issue_pending()
568 	if (vchan_issue_pending(&jzchan->vchan) && !jzchan->desc)  in jz4780_dma_issue_pending()
571 	spin_unlock_irqrestore(&jzchan->vchan.lock, flags);  in jz4780_dma_issue_pending()
581 	spin_lock_irqsave(&jzchan->vchan.lock, flags);  in jz4780_dma_terminate_all()
583 	/* Clear the DMA status and stop the transfer. */  in jz4780_dma_terminate_all()
584 	jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0);  in jz4780_dma_terminate_all()
585 	if (jzchan->desc) {  in jz4780_dma_terminate_all()
586 		vchan_terminate_vdesc(&jzchan->desc->vdesc);  in jz4780_dma_terminate_all()
587 		jzchan->desc = NULL;  in jz4780_dma_terminate_all()
590 	jz4780_dma_chan_disable(jzdma, jzchan->id);  in jz4780_dma_terminate_all()
592 	vchan_get_all_descriptors(&jzchan->vchan, &head);  in jz4780_dma_terminate_all()
594 	spin_unlock_irqrestore(&jzchan->vchan.lock, flags);  in jz4780_dma_terminate_all()
596 	vchan_dma_desc_free_list(&jzchan->vchan, &head);  in jz4780_dma_terminate_all()
605 	vchan_synchronize(&jzchan->vchan);  in jz4780_dma_synchronize()
606 	jz4780_dma_chan_disable(jzdma, jzchan->id);  in jz4780_dma_synchronize()
614 	if ((config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)  in jz4780_dma_config()
615 	   || (config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES))  in jz4780_dma_config()
616 		return -EINVAL;  in jz4780_dma_config()
619 	memcpy(&jzchan->config, config, sizeof(jzchan->config));  in jz4780_dma_config()
631 	for (i = next_sg; i < desc->count; i++)  in jz4780_dma_desc_residue()
632 		count += desc->desc[i].dtc & GENMASK(23, 0);  in jz4780_dma_desc_residue()
635 		count += jz4780_dma_chn_readl(jzdma, jzchan->id,  in jz4780_dma_desc_residue()
638 	return count << jzchan->transfer_shift;  in jz4780_dma_desc_residue()
650 	spin_lock_irqsave(&jzchan->vchan.lock, flags);  in jz4780_dma_tx_status()
656 	vdesc = vchan_find_desc(&jzchan->vchan, cookie);  in jz4780_dma_tx_status()
661 	} else if (cookie == jzchan->desc->vdesc.tx.cookie) {  in jz4780_dma_tx_status()
662 		residue = jz4780_dma_desc_residue(jzchan, jzchan->desc,  in jz4780_dma_tx_status()
663 					jzchan->curr_hwdesc + 1);  in jz4780_dma_tx_status()
667 	if (vdesc && jzchan->desc && vdesc == &jzchan->desc->vdesc  in jz4780_dma_tx_status()
668 	    && jzchan->desc->status & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT))  in jz4780_dma_tx_status()
672 	spin_unlock_irqrestore(&jzchan->vchan.lock, flags);  in jz4780_dma_tx_status()
679 	const unsigned int soc_flags = jzdma->soc_data->flags;  in jz4780_dma_chan_irq()
680 	struct jz4780_dma_desc *desc = jzchan->desc;  in jz4780_dma_chan_irq()
684 	spin_lock(&jzchan->vchan.lock);  in jz4780_dma_chan_irq()
686 	dcs = jz4780_dma_chn_readl(jzdma, jzchan->id, JZ_DMA_REG_DCS);  in jz4780_dma_chan_irq()
687 	jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0);  in jz4780_dma_chan_irq()
690 		dev_warn(&jzchan->vchan.chan.dev->device,  in jz4780_dma_chan_irq()
695 		dev_warn(&jzchan->vchan.chan.dev->device,  in jz4780_dma_chan_irq()
699 	if (jzchan->desc) {  in jz4780_dma_chan_irq()
700 		jzchan->desc->status = dcs;  in jz4780_dma_chan_irq()
703 			if (jzchan->desc->type == DMA_CYCLIC) {  in jz4780_dma_chan_irq()
704 				vchan_cyclic_callback(&jzchan->desc->vdesc);  in jz4780_dma_chan_irq()
709 				    (jzchan->curr_hwdesc + 1 == desc->count)) {  in jz4780_dma_chan_irq()
710 					vchan_cookie_complete(&desc->vdesc);  in jz4780_dma_chan_irq()
711 					jzchan->desc = NULL;  in jz4780_dma_chan_irq()
716 				/* False positive - continue the transfer */  in jz4780_dma_chan_irq()
718 				jz4780_dma_chn_writel(jzdma, jzchan->id,  in jz4780_dma_chan_irq()
724 		dev_err(&jzchan->vchan.chan.dev->device,  in jz4780_dma_chan_irq()
728 	spin_unlock(&jzchan->vchan.lock);  in jz4780_dma_chan_irq()
736 	unsigned int nb_channels = jzdma->soc_data->nb_channels;  in jz4780_dma_irq_handler()
744 		if (jz4780_dma_chan_irq(jzdma, &jzdma->chan[i]))  in jz4780_dma_irq_handler()
763 	jzchan->desc_pool = dma_pool_create(dev_name(&chan->dev->device),  in jz4780_dma_alloc_chan_resources()
764 					    chan->device->dev,  in jz4780_dma_alloc_chan_resources()
767 	if (!jzchan->desc_pool) {  in jz4780_dma_alloc_chan_resources()
768 		dev_err(&chan->dev->device,  in jz4780_dma_alloc_chan_resources()
770 		return -ENOMEM;  in jz4780_dma_alloc_chan_resources()
780 	vchan_free_chan_resources(&jzchan->vchan);  in jz4780_dma_free_chan_resources()
781 	dma_pool_destroy(jzchan->desc_pool);  in jz4780_dma_free_chan_resources()
782 	jzchan->desc_pool = NULL;  in jz4780_dma_free_chan_resources()
792 	if (data->channel > -1) {  in jz4780_dma_filter_fn()
793 		if (data->channel != jzchan->id)  in jz4780_dma_filter_fn()
795 	} else if (jzdma->chan_reserved & BIT(jzchan->id)) {  in jz4780_dma_filter_fn()
799 	jzchan->transfer_type_tx = data->transfer_type_tx;  in jz4780_dma_filter_fn()
800 	jzchan->transfer_type_rx = data->transfer_type_rx;  in jz4780_dma_filter_fn()
808 	struct jz4780_dma_dev *jzdma = ofdma->of_dma_data;  in jz4780_of_dma_xlate()
809 	dma_cap_mask_t mask = jzdma->dma_device.cap_mask;  in jz4780_of_dma_xlate()
812 	if (dma_spec->args_count == 2) {  in jz4780_of_dma_xlate()
813 		data.transfer_type_tx = dma_spec->args[0];  in jz4780_of_dma_xlate()
814 		data.transfer_type_rx = dma_spec->args[0];  in jz4780_of_dma_xlate()
815 		data.channel = dma_spec->args[1];  in jz4780_of_dma_xlate()
816 	} else if (dma_spec->args_count == 3) {  in jz4780_of_dma_xlate()
817 		data.transfer_type_tx = dma_spec->args[0];  in jz4780_of_dma_xlate()
818 		data.transfer_type_rx = dma_spec->args[1];  in jz4780_of_dma_xlate()
819 		data.channel = dma_spec->args[2];  in jz4780_of_dma_xlate()
824 	if (data.channel > -1) {  in jz4780_of_dma_xlate()
825 		if (data.channel >= jzdma->soc_data->nb_channels) {  in jz4780_of_dma_xlate()
826 			dev_err(jzdma->dma_device.dev,  in jz4780_of_dma_xlate()
827 				"device requested non-existent channel %u\n",  in jz4780_of_dma_xlate()
833 		if (!(jzdma->chan_reserved & BIT(data.channel))) {  in jz4780_of_dma_xlate()
834 			dev_err(jzdma->dma_device.dev,  in jz4780_of_dma_xlate()
840 		jzdma->chan[data.channel].transfer_type_tx = data.transfer_type_tx;  in jz4780_of_dma_xlate()
841 		jzdma->chan[data.channel].transfer_type_rx = data.transfer_type_rx;  in jz4780_of_dma_xlate()
844 			&jzdma->chan[data.channel].vchan.chan);  in jz4780_of_dma_xlate()
847 					     ofdma->of_node);  in jz4780_of_dma_xlate()
853 	struct device *dev = &pdev->dev;  in jz4780_dma_probe()
861 	if (!dev->of_node) {  in jz4780_dma_probe()
863 		return -EINVAL;  in jz4780_dma_probe()
868 		return -EINVAL;  in jz4780_dma_probe()
871 			     soc_data->nb_channels), GFP_KERNEL);  in jz4780_dma_probe()
873 		return -ENOMEM;  in jz4780_dma_probe()
875 	jzdma->soc_data = soc_data;  in jz4780_dma_probe()
878 	jzdma->chn_base = devm_platform_ioremap_resource(pdev, 0);  in jz4780_dma_probe()
879 	if (IS_ERR(jzdma->chn_base))  in jz4780_dma_probe()
880 		return PTR_ERR(jzdma->chn_base);  in jz4780_dma_probe()
884 		jzdma->ctrl_base = devm_ioremap_resource(dev, res);  in jz4780_dma_probe()
885 		if (IS_ERR(jzdma->ctrl_base))  in jz4780_dma_probe()
886 			return PTR_ERR(jzdma->ctrl_base);  in jz4780_dma_probe()
887 	} else if (soc_data->flags & JZ_SOC_DATA_ALLOW_LEGACY_DT) {  in jz4780_dma_probe()
889 		 * On JZ4780, if the second memory resource was not supplied,  in jz4780_dma_probe()
893 		jzdma->ctrl_base = jzdma->chn_base + JZ4780_DMA_CTRL_OFFSET;  in jz4780_dma_probe()
896 		return -EINVAL;  in jz4780_dma_probe()
899 	jzdma->clk = devm_clk_get(dev, NULL);  in jz4780_dma_probe()
900 	if (IS_ERR(jzdma->clk)) {  in jz4780_dma_probe()
902 		ret = PTR_ERR(jzdma->clk);  in jz4780_dma_probe()
906 	clk_prepare_enable(jzdma->clk);  in jz4780_dma_probe()
909 	of_property_read_u32_index(dev->of_node, "ingenic,reserved-channels",  in jz4780_dma_probe()
910 				   0, &jzdma->chan_reserved);  in jz4780_dma_probe()
912 	dd = &jzdma->dma_device;  in jz4780_dma_probe()
917 	 * and may be as small as 1 byte, use a safe limit of 2^24-1 bytes to  in jz4780_dma_probe()
918 	 * ensure the 24-bit transfer count in the descriptor cannot overflow.  in jz4780_dma_probe()
922 	dma_cap_set(DMA_MEMCPY, dd->cap_mask);  in jz4780_dma_probe()
923 	dma_cap_set(DMA_SLAVE, dd->cap_mask);  in jz4780_dma_probe()
924 	dma_cap_set(DMA_CYCLIC, dd->cap_mask);  in jz4780_dma_probe()
926 	dd->dev = dev;  in jz4780_dma_probe()
927 	dd->copy_align = DMAENGINE_ALIGN_4_BYTES;  in jz4780_dma_probe()
928 	dd->device_alloc_chan_resources = jz4780_dma_alloc_chan_resources;  in jz4780_dma_probe()
929 	dd->device_free_chan_resources = jz4780_dma_free_chan_resources;  in jz4780_dma_probe()
930 	dd->device_prep_slave_sg = jz4780_dma_prep_slave_sg;  in jz4780_dma_probe()
931 	dd->device_prep_dma_cyclic = jz4780_dma_prep_dma_cyclic;  in jz4780_dma_probe()
932 	dd->device_prep_dma_memcpy = jz4780_dma_prep_dma_memcpy;  in jz4780_dma_probe()
933 	dd->device_config = jz4780_dma_config;  in jz4780_dma_probe()
934 	dd->device_terminate_all = jz4780_dma_terminate_all;  in jz4780_dma_probe()
935 	dd->device_synchronize = jz4780_dma_synchronize;  in jz4780_dma_probe()
936 	dd->device_tx_status = jz4780_dma_tx_status;  in jz4780_dma_probe()
937 	dd->device_issue_pending = jz4780_dma_issue_pending;  in jz4780_dma_probe()
938 	dd->src_addr_widths = JZ_DMA_BUSWIDTHS;  in jz4780_dma_probe()
939 	dd->dst_addr_widths = JZ_DMA_BUSWIDTHS;  in jz4780_dma_probe()
940 	dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);  in jz4780_dma_probe()
941 	dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;  in jz4780_dma_probe()
942 	dd->max_sg_burst = JZ_DMA_MAX_DESC;  in jz4780_dma_probe()
945 	 * Enable DMA controller, mark all channels as not programmable.  in jz4780_dma_probe()
946 	 * Also set the FMSC bit - it increases MSC performance, so it makes  in jz4780_dma_probe()
952 	if (soc_data->flags & JZ_SOC_DATA_PROGRAMMABLE_DMA)  in jz4780_dma_probe()
955 	INIT_LIST_HEAD(&dd->channels);  in jz4780_dma_probe()
957 	for (i = 0; i < soc_data->nb_channels; i++) {  in jz4780_dma_probe()
958 		jzchan = &jzdma->chan[i];  in jz4780_dma_probe()
959 		jzchan->id = i;  in jz4780_dma_probe()
961 		vchan_init(&jzchan->vchan, dd);  in jz4780_dma_probe()
962 		jzchan->vchan.desc_free = jz4780_dma_desc_free;  in jz4780_dma_probe()
977 	jzdma->irq = ret;  in jz4780_dma_probe()
979 	ret = request_irq(jzdma->irq, jz4780_dma_irq_handler, 0, dev_name(dev),  in jz4780_dma_probe()
982 		dev_err(dev, "failed to request IRQ %u!\n", jzdma->irq);  in jz4780_dma_probe()
992 	/* Register with OF DMA helpers. */  in jz4780_dma_probe()
993 	ret = of_dma_controller_register(dev->of_node, jz4780_of_dma_xlate,  in jz4780_dma_probe()
996 		dev_err(dev, "failed to register OF DMA controller\n");  in jz4780_dma_probe()
1000 	dev_info(dev, "JZ4780 DMA controller initialised\n");  in jz4780_dma_probe()
1004 	free_irq(jzdma->irq, jzdma);  in jz4780_dma_probe()
1007 	clk_disable_unprepare(jzdma->clk);  in jz4780_dma_probe()
1016 	of_dma_controller_free(pdev->dev.of_node);  in jz4780_dma_remove()
1018 	clk_disable_unprepare(jzdma->clk);  in jz4780_dma_remove()
1019 	free_irq(jzdma->irq, jzdma);  in jz4780_dma_remove()
1021 	for (i = 0; i < jzdma->soc_data->nb_channels; i++)  in jz4780_dma_remove()
1022 		tasklet_kill(&jzdma->chan[i].vchan.task);  in jz4780_dma_remove()
1108 	{ .compatible = "ingenic,jz4740-dma", .data = &jz4740_dma_soc_data },
1109 	{ .compatible = "ingenic,jz4725b-dma", .data = &jz4725b_dma_soc_data },
1110 	{ .compatible = "ingenic,jz4755-dma", .data = &jz4755_dma_soc_data },
1111 	{ .compatible = "ingenic,jz4760-dma", .data = &jz4760_dma_soc_data },
1112 	{ .compatible = "ingenic,jz4760-mdma", .data = &jz4760_mdma_soc_data },
1113 	{ .compatible = "ingenic,jz4760-bdma", .data = &jz4760_bdma_soc_data },
1114 	{ .compatible = "ingenic,jz4760b-dma", .data = &jz4760b_dma_soc_data },
1115 	{ .compatible = "ingenic,jz4760b-mdma", .data = &jz4760b_mdma_soc_data },
1116 	{ .compatible = "ingenic,jz4760b-bdma", .data = &jz4760b_bdma_soc_data },
1117 	{ .compatible = "ingenic,jz4770-dma", .data = &jz4770_dma_soc_data },
1118 	{ .compatible = "ingenic,jz4780-dma", .data = &jz4780_dma_soc_data },
1119 	{ .compatible = "ingenic,x1000-dma", .data = &x1000_dma_soc_data },
1120 	{ .compatible = "ingenic,x1830-dma", .data = &x1830_dma_soc_data },
1129 		.name	= "jz4780-dma",
1146 MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
1147 MODULE_DESCRIPTION("Ingenic JZ4780 DMA controller driver");