21 static inline u32 qce_read(struct qce_device *qce, u32 offset)  in qce_read()  argument
23 	return readl(qce->base + offset);  in qce_read()
26 static inline void qce_write(struct qce_device *qce, u32 offset, u32 val)  in qce_write()  argument
28 	writel(val, qce->base + offset);  in qce_write()
31 static inline void qce_write_array(struct qce_device *qce, u32 offset,  in qce_write_array()  argument
37 		qce_write(qce, offset + i * sizeof(u32), val[i]);  in qce_write_array()
41 qce_clear_array(struct qce_device *qce, u32 offset, unsigned int len)  in qce_clear_array()  argument
46 		qce_write(qce, offset + i * sizeof(u32), 0);  in qce_clear_array()
49 static u32 qce_config_reg(struct qce_device *qce, int little)  in qce_config_reg()  argument
51 	u32 beats = (qce->burst_size >> 3) - 1;  in qce_config_reg()
52 	u32 pipe_pair = qce->pipe_pair_id;  in qce_config_reg()
81 static void qce_setup_config(struct qce_device *qce)  in qce_setup_config()  argument
86 	config = qce_config_reg(qce, 0);  in qce_setup_config()
89 	qce_write(qce, REG_STATUS, 0);  in qce_setup_config()
90 	qce_write(qce, REG_CONFIG, config);  in qce_setup_config()
93 static inline void qce_crypto_go(struct qce_device *qce, bool result_dump)  in qce_crypto_go()  argument
96 		qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));  in qce_crypto_go()
98 		qce_write(qce, REG_GOPROC, BIT(GO_SHIFT));  in qce_crypto_go()
153 	struct qce_device *qce = tmpl->qce;  in qce_setup_regs_ahash()  local
165 	qce_setup_config(qce);  in qce_setup_regs_ahash()
168 		qce_write(qce, REG_AUTH_SEG_CFG, 0);  in qce_setup_regs_ahash()
169 		qce_write(qce, REG_ENCR_SEG_CFG, 0);  in qce_setup_regs_ahash()
170 		qce_write(qce, REG_ENCR_SEG_SIZE, 0);  in qce_setup_regs_ahash()
171 		qce_clear_array(qce, REG_AUTH_IV0, 16);  in qce_setup_regs_ahash()
172 		qce_clear_array(qce, REG_AUTH_KEY0, 16);  in qce_setup_regs_ahash()
173 		qce_clear_array(qce, REG_AUTH_BYTECNT0, 4);  in qce_setup_regs_ahash()
182 		qce_write_array(qce, REG_AUTH_KEY0, (u32 *)mackey,  in qce_setup_regs_ahash()
195 	qce_write_array(qce, REG_AUTH_IV0, (u32 *)auth, iv_words);  in qce_setup_regs_ahash()
198 		qce_clear_array(qce, REG_AUTH_BYTECNT0, 4);  in qce_setup_regs_ahash()
200 		qce_write_array(qce, REG_AUTH_BYTECNT0,  in qce_setup_regs_ahash()
216 	qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);  in qce_setup_regs_ahash()
217 	qce_write(qce, REG_AUTH_SEG_SIZE, req->nbytes);  in qce_setup_regs_ahash()
218 	qce_write(qce, REG_AUTH_SEG_START, 0);  in qce_setup_regs_ahash()
219 	qce_write(qce, REG_ENCR_SEG_CFG, 0);  in qce_setup_regs_ahash()
220 	qce_write(qce, REG_SEG_SIZE, req->nbytes);  in qce_setup_regs_ahash()
223 	config = qce_config_reg(qce, 1);  in qce_setup_regs_ahash()
224 	qce_write(qce, REG_CONFIG, config);  in qce_setup_regs_ahash()
226 	qce_crypto_go(qce, true);  in qce_setup_regs_ahash()
298 static void qce_xtskey(struct qce_device *qce, const u8 *enckey,  in qce_xtskey()  argument
306 	qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);  in qce_xtskey()
311 	qce_write(qce, REG_ENCR_XTS_DU_SIZE, cryptlen);  in qce_xtskey()
320 	struct qce_device *qce = tmpl->qce;  in qce_setup_regs_skcipher()  local
329 	qce_setup_config(qce);  in qce_setup_regs_skcipher()
339 	qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);  in qce_setup_regs_skcipher()
351 			qce_xtskey(qce, ctx->enc_key, ctx->enc_keylen,  in qce_setup_regs_skcipher()
358 	qce_write_array(qce, REG_ENCR_KEY0, (u32 *)enckey, enckey_words);  in qce_setup_regs_skcipher()
366 		qce_write_array(qce, REG_CNTR0_IV0, (u32 *)enciv, enciv_words);  in qce_setup_regs_skcipher()
372 	qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg);  in qce_setup_regs_skcipher()
373 	qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen);  in qce_setup_regs_skcipher()
374 	qce_write(qce, REG_ENCR_SEG_START, 0);  in qce_setup_regs_skcipher()
377 		qce_write(qce, REG_CNTR_MASK, ~0);  in qce_setup_regs_skcipher()
378 		qce_write(qce, REG_CNTR_MASK0, ~0);  in qce_setup_regs_skcipher()
379 		qce_write(qce, REG_CNTR_MASK1, ~0);  in qce_setup_regs_skcipher()
380 		qce_write(qce, REG_CNTR_MASK2, ~0);  in qce_setup_regs_skcipher()
383 	qce_write(qce, REG_SEG_SIZE, rctx->cryptlen);  in qce_setup_regs_skcipher()
386 	config = qce_config_reg(qce, 1);  in qce_setup_regs_skcipher()
387 	qce_write(qce, REG_CONFIG, config);  in qce_setup_regs_skcipher()
389 	qce_crypto_go(qce, true);  in qce_setup_regs_skcipher()
426 	struct qce_device *qce = tmpl->qce;  in qce_setup_regs_aead()  local
442 	qce_setup_config(qce);  in qce_setup_regs_aead()
446 	qce_write_array(qce, REG_ENCR_KEY0, enckey, enckey_words);  in qce_setup_regs_aead()
450 	qce_write_array(qce, REG_CNTR0_IV0, enciv, enciv_words);  in qce_setup_regs_aead()
454 		qce_write(qce, REG_CNTR3_IV3, iv_last_word + 1);  in qce_setup_regs_aead()
455 		qce_write_array(qce, REG_ENCR_CCM_INT_CNTR0, (u32 *)enciv, enciv_words);  in qce_setup_regs_aead()
456 		qce_write(qce, REG_CNTR_MASK, ~0);  in qce_setup_regs_aead()
457 		qce_write(qce, REG_CNTR_MASK0, ~0);  in qce_setup_regs_aead()
458 		qce_write(qce, REG_CNTR_MASK1, ~0);  in qce_setup_regs_aead()
459 		qce_write(qce, REG_CNTR_MASK2, ~0);  in qce_setup_regs_aead()
463 	qce_clear_array(qce, REG_AUTH_IV0, 16);  in qce_setup_regs_aead()
464 	qce_clear_array(qce, REG_AUTH_KEY0, 16);  in qce_setup_regs_aead()
467 	qce_clear_array(qce, REG_AUTH_BYTECNT0, 4);  in qce_setup_regs_aead()
471 	qce_write_array(qce, REG_AUTH_KEY0, (u32 *)authkey, authkey_words);  in qce_setup_regs_aead()
484 		qce_write_array(qce, REG_AUTH_IV0, (u32 *)authiv, authiv_words);  in qce_setup_regs_aead()
488 		qce_write_array(qce, REG_AUTH_INFO_NONCE0, authnonce, authnonce_words);  in qce_setup_regs_aead()
495 	qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg);  in qce_setup_regs_aead()
512 	qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);  in qce_setup_regs_aead()
518 		qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen + ctx->authsize);  in qce_setup_regs_aead()
520 		qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen);  in qce_setup_regs_aead()
521 	qce_write(qce, REG_ENCR_SEG_START, rctx->assoclen & 0xffff);  in qce_setup_regs_aead()
524 	qce_write(qce, REG_AUTH_SEG_SIZE, totallen);  in qce_setup_regs_aead()
525 	qce_write(qce, REG_AUTH_SEG_START, 0);  in qce_setup_regs_aead()
529 		qce_write(qce, REG_SEG_SIZE, totallen + ctx->authsize);  in qce_setup_regs_aead()
531 		qce_write(qce, REG_SEG_SIZE, totallen);  in qce_setup_regs_aead()
534 	config = qce_config_reg(qce, 1);  in qce_setup_regs_aead()
535 	qce_write(qce, REG_CONFIG, config);  in qce_setup_regs_aead()
538 	qce_crypto_go(qce, !IS_CCM(flags));  in qce_setup_regs_aead()
567 int qce_check_status(struct qce_device *qce, u32 *status)  in qce_check_status()  argument
571 	*status = qce_read(qce, REG_STATUS);  in qce_check_status()
587 void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step)  in qce_get_version()  argument
591 	val = qce_read(qce, REG_VERSION);  in qce_get_version()