19 					int num_vfs)  in cptpf_enable_vfpf_mbox_intr()  argument
30 	ena_bits = ((num_vfs - 1) % 64);  in cptpf_enable_vfpf_mbox_intr()
35 	if (num_vfs > 64) {  in cptpf_enable_vfpf_mbox_intr()
37 		ena_bits = num_vfs - 64 - 1;  in cptpf_enable_vfpf_mbox_intr()
45 					 int num_vfs)  in cptpf_disable_vfpf_mbox_intr()  argument
61 	if (num_vfs > 64) {  in cptpf_disable_vfpf_mbox_intr()
70 					 int num_vfs)  in cptpf_enable_vf_flr_me_intrs()  argument
74 			 INTR_MASK(num_vfs));  in cptpf_enable_vf_flr_me_intrs()
78 			 RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(num_vfs));  in cptpf_enable_vf_flr_me_intrs()
81 			 INTR_MASK(num_vfs));  in cptpf_enable_vf_flr_me_intrs()
84 			 RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(num_vfs));  in cptpf_enable_vf_flr_me_intrs()
86 	if (num_vfs <= 64)  in cptpf_enable_vf_flr_me_intrs()
90 			 INTR_MASK(num_vfs - 64));  in cptpf_enable_vf_flr_me_intrs()
92 			 RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(num_vfs - 64));  in cptpf_enable_vf_flr_me_intrs()
95 			 INTR_MASK(num_vfs - 64));  in cptpf_enable_vf_flr_me_intrs()
97 			 RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(num_vfs - 64));  in cptpf_enable_vf_flr_me_intrs()
101 				       int num_vfs)  in cptpf_disable_vf_flr_me_intrs()  argument
107 			 RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(num_vfs));  in cptpf_disable_vf_flr_me_intrs()
113 			 RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(num_vfs));  in cptpf_disable_vf_flr_me_intrs()
117 	if (num_vfs <= 64)  in cptpf_disable_vf_flr_me_intrs()
121 			 RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(num_vfs - 64));  in cptpf_disable_vf_flr_me_intrs()
126 			 RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(num_vfs - 64));  in cptpf_disable_vf_flr_me_intrs()
234 				       int num_vfs)  in cptpf_unregister_vfpf_intr()  argument
236 	cptpf_disable_vfpf_mbox_intr(cptpf, num_vfs);  in cptpf_unregister_vfpf_intr()
237 	cptpf_disable_vf_flr_me_intrs(cptpf, num_vfs);  in cptpf_unregister_vfpf_intr()
240 static int cptpf_register_vfpf_intr(struct otx2_cptpf_dev *cptpf, int num_vfs)  in cptpf_register_vfpf_intr()  argument
272 	if (num_vfs > 64) {  in cptpf_register_vfpf_intr()
300 	cptpf_enable_vfpf_mbox_intr(cptpf, num_vfs);  in cptpf_register_vfpf_intr()
301 	cptpf_enable_vf_flr_me_intrs(cptpf, num_vfs);  in cptpf_register_vfpf_intr()
332 static int cptpf_flr_wq_init(struct otx2_cptpf_dev *cptpf, int num_vfs)  in cptpf_flr_wq_init()  argument
340 	cptpf->flr_work = kcalloc(num_vfs, sizeof(struct cptpf_flr_work),  in cptpf_flr_wq_init()
345 	for (vf = 0; vf < num_vfs; vf++) {  in cptpf_flr_wq_init()
356 static int cptpf_vfpf_mbox_init(struct otx2_cptpf_dev *cptpf, int num_vfs)  in cptpf_vfpf_mbox_init()  argument
388 			     num_vfs);  in cptpf_vfpf_mbox_init()
392 	for (i = 0; i < num_vfs; i++) {  in cptpf_vfpf_mbox_init()
671 	int num_vfs = pci_num_vf(pdev);  in cptpf_sriov_disable()  local
673 	if (!num_vfs)  in cptpf_sriov_disable()
677 	cptpf_unregister_vfpf_intr(cptpf, num_vfs);  in cptpf_sriov_disable()
686 static int cptpf_sriov_enable(struct pci_dev *pdev, int num_vfs)  in cptpf_sriov_enable()  argument
692 	ret = cptpf_vfpf_mbox_init(cptpf, num_vfs);  in cptpf_sriov_enable()
696 	ret = cptpf_flr_wq_init(cptpf, num_vfs);  in cptpf_sriov_enable()
700 	ret = cptpf_register_vfpf_intr(cptpf, num_vfs);  in cptpf_sriov_enable()
713 	cptpf->enabled_vfs = num_vfs;  in cptpf_sriov_enable()
714 	ret = pci_enable_sriov(pdev, num_vfs);  in cptpf_sriov_enable()
718 	dev_notice(&cptpf->pdev->dev, "VFs enabled: %d\n", num_vfs);  in cptpf_sriov_enable()
721 	return num_vfs;  in cptpf_sriov_enable()
724 	cptpf_unregister_vfpf_intr(cptpf, num_vfs);  in cptpf_sriov_enable()
733 static int otx2_cptpf_sriov_configure(struct pci_dev *pdev, int num_vfs)  in otx2_cptpf_sriov_configure()  argument
735 	if (num_vfs > 0) {  in otx2_cptpf_sriov_configure()
736 		return cptpf_sriov_enable(pdev, num_vfs);  in otx2_cptpf_sriov_configure()