36 #define AE(handle, ae) ((handle)->hal_handle->aes[ae])  argument
70 			  unsigned char ae, unsigned int ctx_mask)  in qat_hal_set_live_ctx()  argument
72 	AE(handle, ae).live_ctx_mask = ctx_mask;  in qat_hal_set_live_ctx()
77 			     unsigned char ae, unsigned int csr)  in qat_hal_rd_ae_csr()  argument
83 		value = GET_AE_CSR(handle, ae, csr);  in qat_hal_rd_ae_csr()
84 		if (!(GET_AE_CSR(handle, ae, LOCAL_CSR_STATUS) & LCS_STATUS))  in qat_hal_rd_ae_csr()
93 			     unsigned char ae, unsigned int csr,  in qat_hal_wr_ae_csr()  argument
99 		SET_AE_CSR(handle, ae, csr, value);  in qat_hal_wr_ae_csr()
100 		if (!(GET_AE_CSR(handle, ae, LOCAL_CSR_STATUS) & LCS_STATUS))  in qat_hal_wr_ae_csr()
109 				     unsigned char ae, unsigned char ctx,  in qat_hal_get_wakeup_event()  argument
114 	cur_ctx = qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER);  in qat_hal_get_wakeup_event()
115 	qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx);  in qat_hal_get_wakeup_event()
116 	*events = qat_hal_rd_ae_csr(handle, ae, CTX_WAKEUP_EVENTS_INDIRECT);  in qat_hal_get_wakeup_event()
117 	qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx);  in qat_hal_get_wakeup_event()
121 			       unsigned char ae, unsigned int cycles,  in qat_hal_wait_cycles()  argument
129 	base_cnt = qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT);  in qat_hal_wait_cycles()
133 			csr = qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS);  in qat_hal_wait_cycles()
135 		cur_cnt = qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT);  in qat_hal_wait_cycles()
157 			    unsigned char ae, unsigned char mode)  in qat_hal_set_ae_ctx_mode()  argument
167 	csr = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);  in qat_hal_set_ae_ctx_mode()
172 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, new_csr);  in qat_hal_set_ae_ctx_mode()
177 			   unsigned char ae, unsigned char mode)  in qat_hal_set_ae_nn_mode()  argument
181 	csr = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);  in qat_hal_set_ae_nn_mode()
189 		qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, new_csr);  in qat_hal_set_ae_nn_mode()
195 			   unsigned char ae, enum icp_qat_uof_regtype lm_type,  in qat_hal_set_ae_lm_mode()  argument
200 	csr = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);  in qat_hal_set_ae_lm_mode()
229 		qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, new_csr);  in qat_hal_set_ae_lm_mode()
234 				unsigned char ae, unsigned char mode)  in qat_hal_set_ae_tindex_mode()  argument
238 	csr = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);  in qat_hal_set_ae_tindex_mode()
244 		qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, new_csr);  in qat_hal_set_ae_tindex_mode()
314 				unsigned char ae, unsigned int ctx_mask,  in qat_hal_wr_indr_csr()  argument
319 	cur_ctx = qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER);  in qat_hal_wr_indr_csr()
324 		qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx);  in qat_hal_wr_indr_csr()
325 		qat_hal_wr_ae_csr(handle, ae, ae_csr, csr_val);  in qat_hal_wr_indr_csr()
328 	qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx);  in qat_hal_wr_indr_csr()
332 				unsigned char ae, unsigned char ctx,  in qat_hal_rd_indr_csr()  argument
337 	cur_ctx = qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER);  in qat_hal_rd_indr_csr()
338 	qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx);  in qat_hal_rd_indr_csr()
339 	csr_val = qat_hal_rd_ae_csr(handle, ae, ae_csr);  in qat_hal_rd_indr_csr()
340 	qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx);  in qat_hal_rd_indr_csr()
346 				  unsigned char ae, unsigned int ctx_mask,  in qat_hal_put_sig_event()  argument
351 	cur_ctx = qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER);  in qat_hal_put_sig_event()
355 		qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx);  in qat_hal_put_sig_event()
356 		qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_INDIRECT, events);  in qat_hal_put_sig_event()
358 	qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx);  in qat_hal_put_sig_event()
362 				     unsigned char ae, unsigned int ctx_mask,  in qat_hal_put_wakeup_event()  argument
367 	cur_ctx = qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER);  in qat_hal_put_wakeup_event()
371 		qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx);  in qat_hal_put_wakeup_event()
372 		qat_hal_wr_ae_csr(handle, ae, CTX_WAKEUP_EVENTS_INDIRECT,  in qat_hal_put_wakeup_event()
375 	qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx);  in qat_hal_put_wakeup_event()
382 	unsigned char ae;  in qat_hal_check_ae_alive()  local
385 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {  in qat_hal_check_ae_alive()
386 		base_cnt = qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT);  in qat_hal_check_ae_alive()
390 			cur_cnt = qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT);  in qat_hal_check_ae_alive()
395 			pr_err("QAT: AE%d is inactive!!\n", ae);  in qat_hal_check_ae_alive()
404 			    unsigned int ae)  in qat_hal_check_ae_active()  argument
408 	enable = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);  in qat_hal_check_ae_active()
409 	active = qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS);  in qat_hal_check_ae_active()
421 	unsigned char ae;  in qat_hal_reset_timestamp()  local
430 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {  in qat_hal_reset_timestamp()
431 		qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_LOW, 0);  in qat_hal_reset_timestamp()
432 		qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_HIGH, 0);  in qat_hal_reset_timestamp()
479 	unsigned char ae = 0;  in qat_hal_clr_reset()  local
501 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {  in qat_hal_clr_reset()
502 		qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES,  in qat_hal_clr_reset()
504 		qat_hal_wr_indr_csr(handle, ae, ICP_QAT_UCLO_AE_ALL_CTX,  in qat_hal_clr_reset()
508 		qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, INIT_CTX_ARB_VALUE);  in qat_hal_clr_reset()
509 		qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, INIT_CCENABLE_VALUE);  in qat_hal_clr_reset()
510 		qat_hal_put_wakeup_event(handle, ae,  in qat_hal_clr_reset()
513 		qat_hal_put_sig_event(handle, ae,  in qat_hal_clr_reset()
530 				unsigned char ae, unsigned int ctx_mask)  in qat_hal_disable_ctx()  argument
534 	ctx = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);  in qat_hal_disable_ctx()
537 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx);  in qat_hal_disable_ctx()
571 		       unsigned char ae, unsigned int uaddr,  in qat_hal_wr_uwords()  argument
577 	ustore_addr = qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS);  in qat_hal_wr_uwords()
579 	qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr);  in qat_hal_wr_uwords()
587 		qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_LOWER, uwrd_lo);  in qat_hal_wr_uwords()
588 		qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_UPPER, uwrd_hi);  in qat_hal_wr_uwords()
590 	qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr);  in qat_hal_wr_uwords()
594 			       unsigned char ae, unsigned int ctx_mask)  in qat_hal_enable_ctx()  argument
598 	ctx = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);  in qat_hal_enable_ctx()
602 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx);  in qat_hal_enable_ctx()
608 	unsigned char ae;  in qat_hal_clear_xfer()  local
611 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {  in qat_hal_clear_xfer()
613 			qat_hal_init_rd_xfer(handle, ae, 0, ICP_SR_RD_ABS,  in qat_hal_clear_xfer()
615 			qat_hal_init_rd_xfer(handle, ae, 0, ICP_DR_RD_ABS,  in qat_hal_clear_xfer()
624 	unsigned char ae;  in qat_hal_clear_gpr()  local
631 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {  in qat_hal_clear_gpr()
632 		csr_val = qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL);  in qat_hal_clear_gpr()
634 		qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, csr_val);  in qat_hal_clear_gpr()
635 		csr_val = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);  in qat_hal_clear_gpr()
640 		qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, csr_val);  in qat_hal_clear_gpr()
641 		qat_hal_wr_uwords(handle, ae, 0, ARRAY_SIZE(inst),  in qat_hal_clear_gpr()
643 		qat_hal_wr_indr_csr(handle, ae, ctx_mask, CTX_STS_INDIRECT,  in qat_hal_clear_gpr()
646 		savctx = qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS);  in qat_hal_clear_gpr()
647 		qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, 0);  in qat_hal_clear_gpr()
648 		qat_hal_put_wakeup_event(handle, ae, ctx_mask, XCWE_VOLUNTARY);  in qat_hal_clear_gpr()
649 		qat_hal_wr_indr_csr(handle, ae, ctx_mask,  in qat_hal_clear_gpr()
651 		qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, 0);  in qat_hal_clear_gpr()
652 		qat_hal_enable_ctx(handle, ae, ctx_mask);  in qat_hal_clear_gpr()
654 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {  in qat_hal_clear_gpr()
657 			ret = qat_hal_wait_cycles(handle, ae, 20, 1);  in qat_hal_clear_gpr()
661 			pr_err("QAT: clear GPR of AE %d failed", ae);  in qat_hal_clear_gpr()
664 		qat_hal_disable_ctx(handle, ae, ctx_mask);  in qat_hal_clear_gpr()
665 		qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS,  in qat_hal_clear_gpr()
667 		qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES,  in qat_hal_clear_gpr()
669 		qat_hal_wr_indr_csr(handle, ae, ctx_mask, CTX_STS_INDIRECT,  in qat_hal_clear_gpr()
672 		qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, INIT_CTX_ARB_VALUE);  in qat_hal_clear_gpr()
673 		qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, INIT_CCENABLE_VALUE);  in qat_hal_clear_gpr()
674 		qat_hal_put_wakeup_event(handle, ae, ctx_mask,  in qat_hal_clear_gpr()
676 		qat_hal_put_sig_event(handle, ae, ctx_mask,  in qat_hal_clear_gpr()
692 	unsigned char ae = 0;  in qat_hal_chip_init()  local
801 	for_each_set_bit(ae, &ae_mask, ICP_QAT_UCLO_MAX_AE) {  in qat_hal_chip_init()
802 		handle->hal_handle->aes[ae].free_addr = 0;  in qat_hal_chip_init()
803 		handle->hal_handle->aes[ae].free_size =  in qat_hal_chip_init()
805 		handle->hal_handle->aes[ae].ustore_size =  in qat_hal_chip_init()
807 		handle->hal_handle->aes[ae].live_ctx_mask =  in qat_hal_chip_init()
809 		max_en_ae_id = ae;  in qat_hal_chip_init()
814 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {  in qat_hal_chip_init()
815 		csr_val = qat_hal_rd_ae_csr(handle, ae, SIGNATURE_ENABLE);  in qat_hal_chip_init()
817 		qat_hal_wr_ae_csr(handle, ae, SIGNATURE_ENABLE, csr_val);  in qat_hal_chip_init()
891 	unsigned char ae;  in qat_hal_start()  local
909 		for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {  in qat_hal_start()
910 			qat_hal_put_wakeup_event(handle, ae, 0, wakeup_val);  in qat_hal_start()
911 			qat_hal_enable_ctx(handle, ae, ICP_QAT_UCLO_AE_ALL_CTX);  in qat_hal_start()
918 void qat_hal_stop(struct icp_qat_fw_loader_handle *handle, unsigned char ae,  in qat_hal_stop()  argument
922 		qat_hal_disable_ctx(handle, ae, ctx_mask);  in qat_hal_stop()
926 		    unsigned char ae, unsigned int ctx_mask, unsigned int upc)  in qat_hal_set_pc()  argument
928 	qat_hal_wr_indr_csr(handle, ae, ctx_mask, CTX_STS_INDIRECT,  in qat_hal_set_pc()
933 			       unsigned char ae, unsigned int uaddr,  in qat_hal_get_uwords()  argument
939 	misc_control = qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL);  in qat_hal_get_uwords()
940 	qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL,  in qat_hal_get_uwords()
942 	ustore_addr = qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS);  in qat_hal_get_uwords()
945 		qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr);  in qat_hal_get_uwords()
947 		uwrd_lo = qat_hal_rd_ae_csr(handle, ae, USTORE_DATA_LOWER);  in qat_hal_get_uwords()
948 		uwrd_hi = qat_hal_rd_ae_csr(handle, ae, USTORE_DATA_UPPER);  in qat_hal_get_uwords()
952 	qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, misc_control);  in qat_hal_get_uwords()
953 	qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr);  in qat_hal_get_uwords()
957 		     unsigned char ae, unsigned int uaddr,  in qat_hal_wr_umem()  argument
962 	ustore_addr = qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS);  in qat_hal_wr_umem()
964 	qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr);  in qat_hal_wr_umem()
975 		qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_LOWER, uwrd_lo);  in qat_hal_wr_umem()
976 		qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_UPPER, uwrd_hi);  in qat_hal_wr_umem()
978 	qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr);  in qat_hal_wr_umem()
983 				   unsigned char ae, unsigned char ctx,  in qat_hal_exec_micro_inst()  argument
1006 	ind_lm_addr0 = qat_hal_rd_indr_csr(handle, ae, ctx, LM_ADDR_0_INDIRECT);  in qat_hal_exec_micro_inst()
1007 	ind_lm_addr1 = qat_hal_rd_indr_csr(handle, ae, ctx, LM_ADDR_1_INDIRECT);  in qat_hal_exec_micro_inst()
1008 	ind_lm_addr_byte0 = qat_hal_rd_indr_csr(handle, ae, ctx,  in qat_hal_exec_micro_inst()
1010 	ind_lm_addr_byte1 = qat_hal_rd_indr_csr(handle, ae, ctx,  in qat_hal_exec_micro_inst()
1013 		ind_lm_addr2 = qat_hal_rd_indr_csr(handle, ae, ctx,  in qat_hal_exec_micro_inst()
1015 		ind_lm_addr3 = qat_hal_rd_indr_csr(handle, ae, ctx,  in qat_hal_exec_micro_inst()
1017 		ind_lm_addr_byte2 = qat_hal_rd_indr_csr(handle, ae, ctx,  in qat_hal_exec_micro_inst()
1019 		ind_lm_addr_byte3 = qat_hal_rd_indr_csr(handle, ae, ctx,  in qat_hal_exec_micro_inst()
1021 		ind_t_index = qat_hal_rd_indr_csr(handle, ae, ctx,  in qat_hal_exec_micro_inst()
1023 		ind_t_index_byte = qat_hal_rd_indr_csr(handle, ae, ctx,  in qat_hal_exec_micro_inst()
1027 		qat_hal_get_uwords(handle, ae, 0, inst_num, savuwords);  in qat_hal_exec_micro_inst()
1028 	qat_hal_get_wakeup_event(handle, ae, ctx, &wakeup_events);  in qat_hal_exec_micro_inst()
1029 	savpc = qat_hal_rd_indr_csr(handle, ae, ctx, CTX_STS_INDIRECT);  in qat_hal_exec_micro_inst()
1031 	ctx_enables = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);  in qat_hal_exec_micro_inst()
1033 	savcc = qat_hal_rd_ae_csr(handle, ae, CC_ENABLE);  in qat_hal_exec_micro_inst()
1034 	savctx = qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS);  in qat_hal_exec_micro_inst()
1035 	ctxarb_ctl = qat_hal_rd_ae_csr(handle, ae, CTX_ARB_CNTL);  in qat_hal_exec_micro_inst()
1036 	ind_cnt_sig = qat_hal_rd_indr_csr(handle, ae, ctx,  in qat_hal_exec_micro_inst()
1038 	ind_sig = qat_hal_rd_indr_csr(handle, ae, ctx,  in qat_hal_exec_micro_inst()
1040 	act_sig = qat_hal_rd_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE);  in qat_hal_exec_micro_inst()
1042 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_exec_micro_inst()
1043 	qat_hal_wr_uwords(handle, ae, 0, inst_num, micro_inst);  in qat_hal_exec_micro_inst()
1044 	qat_hal_wr_indr_csr(handle, ae, (1 << ctx), CTX_STS_INDIRECT, 0);  in qat_hal_exec_micro_inst()
1045 	qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, ctx & ACS_ACNO);  in qat_hal_exec_micro_inst()
1047 		qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, savcc & 0xffffdfff);  in qat_hal_exec_micro_inst()
1048 	qat_hal_put_wakeup_event(handle, ae, (1 << ctx), XCWE_VOLUNTARY);  in qat_hal_exec_micro_inst()
1049 	qat_hal_wr_indr_csr(handle, ae, (1 << ctx), CTX_SIG_EVENTS_INDIRECT, 0);  in qat_hal_exec_micro_inst()
1050 	qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, 0);  in qat_hal_exec_micro_inst()
1051 	qat_hal_enable_ctx(handle, ae, (1 << ctx));  in qat_hal_exec_micro_inst()
1053 	if (qat_hal_wait_cycles(handle, ae, max_cycle, 1) != 0)  in qat_hal_exec_micro_inst()
1058 		ctx_status = qat_hal_rd_indr_csr(handle, ae, ctx,  in qat_hal_exec_micro_inst()
1063 	qat_hal_disable_ctx(handle, ae, (1 << ctx));  in qat_hal_exec_micro_inst()
1065 		qat_hal_wr_uwords(handle, ae, 0, inst_num, savuwords);  in qat_hal_exec_micro_inst()
1066 	qat_hal_put_wakeup_event(handle, ae, (1 << ctx), wakeup_events);  in qat_hal_exec_micro_inst()
1067 	qat_hal_wr_indr_csr(handle, ae, (1 << ctx), CTX_STS_INDIRECT,  in qat_hal_exec_micro_inst()
1069 	csr_val = qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL);  in qat_hal_exec_micro_inst()
1071 	qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, newcsr_val);  in qat_hal_exec_micro_inst()
1072 	qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, savcc);  in qat_hal_exec_micro_inst()
1073 	qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, savctx & ACS_ACNO);  in qat_hal_exec_micro_inst()
1074 	qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, ctxarb_ctl);  in qat_hal_exec_micro_inst()
1075 	qat_hal_wr_indr_csr(handle, ae, (1 << ctx),  in qat_hal_exec_micro_inst()
1077 	qat_hal_wr_indr_csr(handle, ae, (1 << ctx),  in qat_hal_exec_micro_inst()
1079 	qat_hal_wr_indr_csr(handle, ae, (1 << ctx),  in qat_hal_exec_micro_inst()
1081 	qat_hal_wr_indr_csr(handle, ae, (1 << ctx),  in qat_hal_exec_micro_inst()
1084 		qat_hal_wr_indr_csr(handle, ae, BIT(ctx), LM_ADDR_2_INDIRECT,  in qat_hal_exec_micro_inst()
1086 		qat_hal_wr_indr_csr(handle, ae, BIT(ctx), LM_ADDR_3_INDIRECT,  in qat_hal_exec_micro_inst()
1088 		qat_hal_wr_indr_csr(handle, ae, BIT(ctx),  in qat_hal_exec_micro_inst()
1091 		qat_hal_wr_indr_csr(handle, ae, BIT(ctx),  in qat_hal_exec_micro_inst()
1094 		qat_hal_wr_indr_csr(handle, ae, BIT(ctx),  in qat_hal_exec_micro_inst()
1096 		qat_hal_wr_indr_csr(handle, ae, BIT(ctx),  in qat_hal_exec_micro_inst()
1100 	qat_hal_wr_indr_csr(handle, ae, (1 << ctx),  in qat_hal_exec_micro_inst()
1102 	qat_hal_wr_indr_csr(handle, ae, (1 << ctx),  in qat_hal_exec_micro_inst()
1104 	qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, act_sig);  in qat_hal_exec_micro_inst()
1105 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_exec_micro_inst()
1111 			      unsigned char ae, unsigned char ctx,  in qat_hal_rd_rel_reg()  argument
1134 	savctx = qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS);  in qat_hal_rd_rel_reg()
1135 	ctxarb_cntl = qat_hal_rd_ae_csr(handle, ae, CTX_ARB_CNTL);  in qat_hal_rd_rel_reg()
1136 	ctx_enables = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);  in qat_hal_rd_rel_reg()
1139 		qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS,  in qat_hal_rd_rel_reg()
1141 	qat_hal_get_uwords(handle, ae, 0, 1, &savuword);  in qat_hal_rd_rel_reg()
1142 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_rd_rel_reg()
1143 	ustore_addr = qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS);  in qat_hal_rd_rel_reg()
1145 	qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr);  in qat_hal_rd_rel_reg()
1149 	qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_LOWER, uwrd_lo);  in qat_hal_rd_rel_reg()
1150 	qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_UPPER, uwrd_hi);  in qat_hal_rd_rel_reg()
1151 	qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr);  in qat_hal_rd_rel_reg()
1153 	qat_hal_wait_cycles(handle, ae, 0x8, 0);  in qat_hal_rd_rel_reg()
1159 	*data = qat_hal_rd_ae_csr(handle, ae, ALU_OUT);  in qat_hal_rd_rel_reg()
1160 	qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr);  in qat_hal_rd_rel_reg()
1161 	qat_hal_wr_uwords(handle, ae, 0, 1, &savuword);  in qat_hal_rd_rel_reg()
1163 		qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS,  in qat_hal_rd_rel_reg()
1165 	qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, ctxarb_cntl);  in qat_hal_rd_rel_reg()
1166 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_rd_rel_reg()
1172 			      unsigned char ae, unsigned char ctx,  in qat_hal_wr_rel_reg()  argument
1214 	return qat_hal_exec_micro_inst(handle, ae, ctx, insts, num_inst,  in qat_hal_wr_rel_reg()
1253 				      unsigned char ae, unsigned char ctx,  in qat_hal_exec_micro_init_lm()  argument
1262 		qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0, &gpra0);  in qat_hal_exec_micro_init_lm()
1263 		qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x1, &gpra1);  in qat_hal_exec_micro_init_lm()
1264 		qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x2, &gpra2);  in qat_hal_exec_micro_init_lm()
1265 		qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0, &gprb0);  in qat_hal_exec_micro_init_lm()
1266 		qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0x1, &gprb1);  in qat_hal_exec_micro_init_lm()
1269 	stat = qat_hal_exec_micro_inst(handle, ae, ctx, micro_inst, inst_num, 1,  in qat_hal_exec_micro_init_lm()
1273 	qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0, gpra0);  in qat_hal_exec_micro_init_lm()
1274 	qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x1, gpra1);  in qat_hal_exec_micro_init_lm()
1275 	qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x2, gpra2);  in qat_hal_exec_micro_init_lm()
1276 	qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0, gprb0);  in qat_hal_exec_micro_init_lm()
1277 	qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0x1, gprb1);  in qat_hal_exec_micro_init_lm()
1283 			unsigned char ae,  in qat_hal_batch_wr_lm()  argument
1305 		ae = plm_init->ae;  in qat_hal_batch_wr_lm()
1317 		stat = qat_hal_exec_micro_init_lm(handle, ae, 0, &first_exec,  in qat_hal_batch_wr_lm()
1326 				   unsigned char ae, unsigned char ctx,  in qat_hal_put_rel_rd_xfer()  argument
1336 	ctx_enables = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);  in qat_hal_put_rel_rd_xfer()
1353 		SET_AE_XFER(handle, ae, reg_addr, val);  in qat_hal_put_rel_rd_xfer()
1357 		SET_AE_XFER(handle, ae, (reg_addr + dr_offset), val);  in qat_hal_put_rel_rd_xfer()
1367 				   unsigned char ae, unsigned char ctx,  in qat_hal_put_rel_wr_xfer()  argument
1386 	ctx_enables = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);  in qat_hal_put_rel_wr_xfer()
1403 	status = qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPB_REL, gprnum, &gprval);  in qat_hal_put_rel_wr_xfer()
1421 	status = qat_hal_exec_micro_inst(handle, ae, ctx, micro_inst, num_inst,  in qat_hal_put_rel_wr_xfer()
1423 	qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPB_REL, gprnum, gprval);  in qat_hal_put_rel_wr_xfer()
1428 			      unsigned char ae, unsigned char ctx,  in qat_hal_put_rel_nn()  argument
1434 	ctx_enables = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);  in qat_hal_put_rel_nn()
1436 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables | CE_NN_MODE);  in qat_hal_put_rel_nn()
1438 	stat = qat_hal_put_rel_wr_xfer(handle, ae, ctx, ICP_NEIGH_REL, nn, val);  in qat_hal_put_rel_nn()
1439 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_put_rel_nn()
1444 				      *handle, unsigned char ae,  in qat_hal_convert_abs_to_rel()  argument
1451 	ctx_enables = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);  in qat_hal_convert_abs_to_rel()
1465 		     unsigned char ae, unsigned long ctx_mask,  in qat_hal_init_gpr()  argument
1479 			qat_hal_convert_abs_to_rel(handle, ae, reg_num, &reg,  in qat_hal_init_gpr()
1488 		stat = qat_hal_wr_rel_reg(handle, ae, ctx, type, reg, regdata);  in qat_hal_init_gpr()
1499 			 unsigned char ae, unsigned long ctx_mask,  in qat_hal_init_wr_xfer()  argument
1513 			qat_hal_convert_abs_to_rel(handle, ae, reg_num, &reg,  in qat_hal_init_wr_xfer()
1522 		stat = qat_hal_put_rel_wr_xfer(handle, ae, ctx, type, reg,  in qat_hal_init_wr_xfer()
1534 			 unsigned char ae, unsigned long ctx_mask,  in qat_hal_init_rd_xfer()  argument
1548 			qat_hal_convert_abs_to_rel(handle, ae, reg_num, &reg,  in qat_hal_init_rd_xfer()
1557 		stat = qat_hal_put_rel_rd_xfer(handle, ae, ctx, type, reg,  in qat_hal_init_rd_xfer()
1569 		    unsigned char ae, unsigned long ctx_mask,  in qat_hal_init_nn()  argument
1586 		stat = qat_hal_put_rel_nn(handle, ae, ctx, reg_num, regdata);  in qat_hal_init_nn()