Lines Matching refs:u32
59 u32 num_entries;
107 u32 instances;
111 u32 arb_cfg;
112 u32 arb_offset;
113 u32 wt2sam_offset;
117 u32 admin_msg_ur;
118 u32 admin_msg_lr;
119 u32 mailbox_offset;
123 u64 (*build_csr_ring_base_addr)(dma_addr_t addr, u32 size);
124 u32 (*read_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
125 u32 ring);
126 void (*write_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
127 u32 ring, u32 value);
128 u32 (*read_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
129 u32 ring);
130 void (*write_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
131 u32 ring, u32 value);
132 u32 (*read_csr_e_stat)(void __iomem *csr_base_addr, u32 bank);
133 void (*write_csr_ring_config)(void __iomem *csr_base_addr, u32 bank,
134 u32 ring, u32 value);
135 void (*write_csr_ring_base)(void __iomem *csr_base_addr, u32 bank,
136 u32 ring, dma_addr_t addr);
137 void (*write_csr_int_flag)(void __iomem *csr_base_addr, u32 bank,
138 u32 value);
139 void (*write_csr_int_srcsel)(void __iomem *csr_base_addr, u32 bank);
140 void (*write_csr_int_col_en)(void __iomem *csr_base_addr, u32 bank,
141 u32 value);
142 void (*write_csr_int_col_ctl)(void __iomem *csr_base_addr, u32 bank,
143 u32 value);
145 u32 bank, u32 value);
146 void (*write_csr_ring_srv_arb_en)(void __iomem *csr_base_addr, u32 bank,
147 u32 value);
157 u32 (*get_pf2vf_offset)(u32 i);
158 u32 (*get_vf2pf_offset)(u32 i);
159 void (*enable_vf2pf_interrupts)(void __iomem *pmisc_addr, u32 vf_mask);
161 u32 (*disable_pending_vf2pf_interrupts)(void __iomem *pmisc_addr);
163 u32 pfvf_offset, struct mutex *csr_lock);
165 u32 pfvf_offset, u8 compat_ver);
174 u32 (*get_accel_mask)(struct adf_hw_device_data *self);
175 u32 (*get_ae_mask)(struct adf_hw_device_data *self);
176 u32 (*get_accel_cap)(struct adf_accel_dev *accel_dev);
177 u32 (*get_sram_bar_id)(struct adf_hw_device_data *self);
178 u32 (*get_misc_bar_id)(struct adf_hw_device_data *self);
179 u32 (*get_etr_bar_id)(struct adf_hw_device_data *self);
180 u32 (*get_num_aes)(struct adf_hw_device_data *self);
181 u32 (*get_num_accels)(struct adf_hw_device_data *self);
199 const u32 *(*get_arb_mapping)(struct adf_accel_dev *accel_dev);
208 int (*ring_pair_reset)(struct adf_accel_dev *accel_dev, u32 bank_nr);
211 const char *(*uof_get_name)(struct adf_accel_dev *accel_dev, u32 obj_num);
212 u32 (*uof_get_num_objs)(void);
213 u32 (*uof_get_ae_mask)(struct adf_accel_dev *accel_dev, u32 obj_num);
220 u32 fuses;
221 u32 straps;
222 u32 accel_capabilities_mask;
223 u32 extended_dc_capabilities;
224 u32 clock_frequency;
225 u32 instance_id;
227 u32 ae_mask;
228 u32 admin_ae_mask;
238 u32 num_hb_ctrs;
284 u32 vf_nr;
332 u32 accel_id;