Lines Matching +full:0 +full:x9038
36 * Map all interfaces/rings to register index 0 in eip197_trc_cache_setupvirt()
44 for (i = 0; i < 4; i++) in eip197_trc_cache_setupvirt()
45 writel(0, priv->base + EIP197_FLUE_IFC_LUT(i)); in eip197_trc_cache_setupvirt()
51 for (i = 0; i < priv->config.rings; i++) { in eip197_trc_cache_setupvirt()
52 writel(0, priv->base + EIP197_FLUE_CACHEBASE_LO(i)); in eip197_trc_cache_setupvirt()
53 writel(0, priv->base + EIP197_FLUE_CACHEBASE_HI(i)); in eip197_trc_cache_setupvirt()
57 writel(0, priv->base + EIP197_FLUE_OFFSETS); in eip197_trc_cache_setupvirt()
58 writel(0, priv->base + EIP197_FLUE_ARC4_OFFSET); in eip197_trc_cache_setupvirt()
88 addrlo = 0; in eip197_trc_cache_probe()
89 actbank = min(maxbanks - 1, 0); in eip197_trc_cache_probe()
93 marker = (addrmid ^ 0xabadbabe) & probemask; /* Unique */ in eip197_trc_cache_probe()
97 (addrmid & 0xffff)); in eip197_trc_cache_probe()
106 (addralias & 0xffff)); in eip197_trc_cache_probe()
113 (addrmid & 0xffff)); in eip197_trc_cache_probe()
132 for (i = 0; i < cs_rc_max; i++) { in eip197_trc_cache_clear()
140 if (i == 0) in eip197_trc_cache_clear()
146 writel(0, priv->base + offset + 8); in eip197_trc_cache_clear()
147 writel(0, priv->base + offset + 12); in eip197_trc_cache_clear()
152 for (i = 0; i < cs_ht_wc; i++) in eip197_trc_cache_clear()
153 writel(GENMASK(29, 0), in eip197_trc_cache_clear()
180 writel(0, priv->base + EIP197_TRC_ECCCTRL); in eip197_trc_cache_init()
191 dsize = eip197_trc_cache_probe(priv, maxbanks, 0xffffffff, 32); in eip197_trc_cache_init()
204 asize = eip197_trc_cache_probe(priv, 0, 0x3fffffff, 16) >> 4; in eip197_trc_cache_init()
207 writel(0, priv->base + EIP197_TRC_ECCCTRL); in eip197_trc_cache_init()
249 val = EIP197_TRC_FREECHAIN_HEAD_PTR(0) | in eip197_trc_cache_init()
266 return 0; in eip197_trc_cache_init()
274 for (pe = 0; pe < priv->config.pes; pe++) { in eip197_init_firmware()
277 writel(0, EIP197_PE(priv) + EIP197_PE_ICE_PPTF_CTRL(pe)); in eip197_init_firmware()
288 for (i = 0; i < EIP197_NUM_OF_SCRATCH_BLOCKS; i++) in eip197_init_firmware()
289 writel(0, EIP197_PE(priv) + in eip197_init_firmware()
323 for (i = 0; i < fw->size / sizeof(u32); i++) { in eip197_write_firmware()
352 for (pe = 0; pe < priv->config.pes; pe++) { in poll_fw_ready()
375 for (pe = 0; pe < priv->config.pes; pe++) { in eip197_start_firmware()
377 writel(0, EIP197_PE(priv) + EIP197_PE_ICE_RAM_CTRL(pe)); in eip197_start_firmware()
381 val = 0; in eip197_start_firmware()
390 val = 0; in eip197_start_firmware()
405 if (!poll_fw_ready(priv, 0)) in eip197_start_firmware()
416 int i, j, ret = 0, pe; in eip197_load_firmwares()
417 int ipuesz, ifppsz, minifw = 0; in eip197_load_firmwares()
430 for (i = 0; i < FW_NB; i++) { in eip197_load_firmwares()
452 for (pe = 0; pe < priv->config.pes; pe++) in eip197_load_firmwares()
460 return 0; in eip197_load_firmwares()
466 for (j = 0; j < i; j++) in eip197_load_firmwares()
510 for (i = 0; i < priv->config.rings; i++) { in safexcel_hw_setup_cdesc_rings()
531 writel(GENMASK(5, 0), in safexcel_hw_setup_cdesc_rings()
535 return 0; in safexcel_hw_setup_cdesc_rings()
558 for (i = 0; i < priv->config.rings; i++) { in safexcel_hw_setup_rdesc_rings()
582 writel(GENMASK(7, 0), in safexcel_hw_setup_rdesc_rings()
591 return 0; in safexcel_hw_setup_rdesc_rings()
620 writel(0, EIP197_HIA_AIC_G(priv) + EIP197_HIA_AIC_G_ENABLE_CTRL); in safexcel_hw_init()
623 writel(GENMASK(31, 0), EIP197_HIA_AIC_G(priv) + EIP197_HIA_AIC_G_ACK); in safexcel_hw_init()
626 for (pe = 0; pe < priv->config.pes; pe++) { in safexcel_hw_init()
649 writel(0, EIP197_HIA_DFE_THR(priv) + EIP197_HIA_DFE_THR_CTRL(pe)); in safexcel_hw_init()
662 GENMASK(priv->config.rings - 1, 0), in safexcel_hw_init()
697 writel(0, EIP197_HIA_DSE_THR(priv) + EIP197_HIA_DSE_THR_CTRL(pe)); in safexcel_hw_init()
720 for (i = 0; i < priv->config.rings; i++) { in safexcel_hw_init()
722 writel(GENMASK(31, 0), in safexcel_hw_init()
726 writel(0, EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_CFG); in safexcel_hw_init()
736 writel(0, in safexcel_hw_init()
738 writel(0, in safexcel_hw_init()
746 for (i = 0; i < priv->config.rings; i++) { in safexcel_hw_init()
748 writel(0, EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_CFG); in safexcel_hw_init()
758 writel(0, in safexcel_hw_init()
760 writel(0, in safexcel_hw_init()
768 for (pe = 0; pe < priv->config.pes; pe++) { in safexcel_hw_init()
770 writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0), in safexcel_hw_init()
774 writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0), in safexcel_hw_init()
787 EIP197_PE(priv) + EIP197_PE_EIP96_TOKEN_CTRL2(0)); in safexcel_hw_init()
802 0; in safexcel_hw_init()
824 int ret, nreq = 0, cdesc = 0, rdesc = 0, commands, results; in safexcel_dequeue()
908 return 0; in safexcel_rdesc_check_errors()
916 if (result_data->error_code & 0x4066) { in safexcel_rdesc_check_errors()
924 (BIT(7) | BIT(4) | BIT(3) | BIT(0))) { in safexcel_rdesc_check_errors()
980 int ret = 0; in safexcel_invalidate_cache()
983 cdesc = safexcel_add_cdesc(priv, ring, true, true, 0, 0, 0, ctxr_dma, in safexcel_invalidate_cache()
989 cdesc->control_data.options = 0; in safexcel_invalidate_cache()
994 rdesc = safexcel_add_rdesc(priv, ring, true, true, 0, 0); in safexcel_invalidate_cache()
1016 int ret, i, nreq, ndesc, tot_descs, handled = 0; in safexcel_handle_result_descriptor()
1020 tot_descs = 0; in safexcel_handle_result_descriptor()
1028 for (i = 0; i < nreq; i++) { in safexcel_handle_result_descriptor()
1034 if (ndesc < 0) { in safexcel_handle_result_descriptor()
1114 writel(stat & 0xff, in safexcel_irq_ring()
1153 if (irq < 0) { in safexcel_request_ring_irq()
1160 char irq_name[6] = {0}; /* "ringX\0" */ in safexcel_request_ring_irq()
1166 if (irq < 0) in safexcel_request_ring_irq()
1265 int i, j, ret = 0; in safexcel_register_algorithms()
1267 for (i = 0; i < ARRAY_SIZE(safexcel_algs); i++) { in safexcel_register_algorithms()
1287 return 0; in safexcel_register_algorithms()
1290 for (j = 0; j < i; j++) { in safexcel_register_algorithms()
1312 for (i = 0; i < ARRAY_SIZE(safexcel_algs); i++) { in safexcel_unregister_algorithms()
1404 1, 0); in safexcel_probe_generic()
1415 mask = 0; /* do not swap */ in safexcel_probe_generic()
1479 version = readl(EIP197_PE(priv) + + EIP197_PE_VERSION(0)); in safexcel_probe_generic()
1487 version = readl(EIP197_PE(priv) + EIP197_PE_EIP96_VERSION(0)); in safexcel_probe_generic()
1497 priv->hwconfig.icever = 0; in safexcel_probe_generic()
1498 priv->hwconfig.ocever = 0; in safexcel_probe_generic()
1499 priv->hwconfig.psever = 0; in safexcel_probe_generic()
1502 peopt = readl(EIP197_PE(priv) + EIP197_PE_OPTIONS(0)); in safexcel_probe_generic()
1522 EIP197_PE_ICE_VERSION(0)); in safexcel_probe_generic()
1533 version = readl(EIP197_PE(priv) + EIP197_PE_PSE_VERSION(0)); in safexcel_probe_generic()
1541 EIP197_PE_ICE_VERSION(0)); in safexcel_probe_generic()
1568 for (i = 0; i < EIP197_MAX_RING_AIC; i++) { in safexcel_probe_generic()
1583 EIP197_PE_EIP96_OPTIONS(0)); in safexcel_probe_generic()
1608 if (ret < 0) { in safexcel_probe_generic()
1621 for (i = 0; i < priv->config.rings; i++) { in safexcel_probe_generic()
1622 char wq_name[9] = {0}; in safexcel_probe_generic()
1659 if (irq < 0) { in safexcel_probe_generic()
1679 priv->ring[i].requests = 0; in safexcel_probe_generic()
1689 atomic_set(&priv->ring_used, 0); in safexcel_probe_generic()
1703 return 0; in safexcel_probe_generic()
1706 for (i = 0; i < priv->config.rings; i++) { in safexcel_probe_generic()
1720 for (i = 0; i < priv->config.rings; i++) { in safexcel_hw_reset_rings()
1722 writel(GENMASK(5, 0), EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_STAT); in safexcel_hw_reset_rings()
1723 writel(GENMASK(7, 0), EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_STAT); in safexcel_hw_reset_rings()
1726 writel(0, EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_RING_BASE_ADDR_LO); in safexcel_hw_reset_rings()
1727 writel(0, EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_RING_BASE_ADDR_HI); in safexcel_hw_reset_rings()
1730 writel(0, EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_RING_BASE_ADDR_LO); in safexcel_hw_reset_rings()
1731 writel(0, EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_RING_BASE_ADDR_HI); in safexcel_hw_reset_rings()
1752 priv->base = devm_platform_ioremap_resource(pdev, 0); in safexcel_probe()
1791 ret = safexcel_probe_generic(pdev, priv, 0); in safexcel_probe()
1795 return 0; in safexcel_probe()
1815 for (i = 0; i < priv->config.rings; i++) { in safexcel_remove()
1820 return 0; in safexcel_remove()
1921 priv->base = pcim_iomap_table(pdev)[0]; in safexcel_pci_probe()
1936 (val & 0xff)); in safexcel_pci_probe()
1949 writel(GENMASK(31, 0), in safexcel_pci_probe()
1962 writel(0, priv->base + EIP197_XLX_GPIO_BASE); in safexcel_pci_probe()
1981 for (i = 0; i < priv->config.rings; i++) in safexcel_pci_remove()
1989 PCI_DEVICE_SUB(PCI_VENDOR_ID_XILINX, 0x9038,
1990 0x16ae, 0xc522),