Lines Matching refs:SEC_CONTROL_REG
54 #define SEC_CONTROL_REG 0x301200 macro
428 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
436 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
520 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()
522 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()
538 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()
540 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()
561 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_engine_init()
563 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_engine_init()
638 val1 = readl(qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()
651 writel(val1, qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()
1020 val = readl(qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()
1021 writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()
1022 writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()