1 // SPDX-License-Identifier: GPL-2.0
306 	struct hisi_qm *qm = s->private;  in sec_diff_regs_show()
308 	hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs,  in sec_diff_regs_show()
330 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)");
338 		return -EINVAL;  in sec_ctx_q_num_set()
342 		return -EINVAL;  in sec_ctx_q_num_set()
346 		return -EINVAL;  in sec_ctx_q_num_set()
367 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
398 	cap_val_h = qm->cap_tables.dev_cap_table[high].cap_val;  in sec_get_alg_bitmap()
399 	cap_val_l = qm->cap_tables.dev_cap_table[low].cap_val;  in sec_get_alg_bitmap()
428 	reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);  in sec_set_endian()
436 	writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);  in sec_set_endian()
443 	if (qm->ver > QM_HW_V2) {  in sec_engine_sva_config()
444 		reg = readl_relaxed(qm->io_base +  in sec_engine_sva_config()
447 		writel_relaxed(reg, qm->io_base +  in sec_engine_sva_config()
450 		reg = readl_relaxed(qm->io_base +  in sec_engine_sva_config()
454 		writel_relaxed(reg, qm->io_base +  in sec_engine_sva_config()
457 		reg = readl_relaxed(qm->io_base +  in sec_engine_sva_config()
460 		writel_relaxed(reg, qm->io_base +  in sec_engine_sva_config()
462 		reg = readl_relaxed(qm->io_base +  in sec_engine_sva_config()
465 		if (qm->use_sva)  in sec_engine_sva_config()
469 		writel_relaxed(reg, qm->io_base +  in sec_engine_sva_config()
479 	if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))  in sec_open_sva_prefetch()
483 	val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG);  in sec_open_sva_prefetch()
485 	writel(val, qm->io_base + SEC_PREFETCH_CFG);  in sec_open_sva_prefetch()
487 	ret = readl_relaxed_poll_timeout(qm->io_base + SEC_PREFETCH_CFG,  in sec_open_sva_prefetch()
491 		pci_err(qm->pdev, "failed to open sva prefetch\n");  in sec_open_sva_prefetch()
499 	if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))  in sec_close_sva_prefetch()
502 	val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG);  in sec_close_sva_prefetch()
504 	writel(val, qm->io_base + SEC_PREFETCH_CFG);  in sec_close_sva_prefetch()
506 	ret = readl_relaxed_poll_timeout(qm->io_base + SEC_SVA_TRANS,  in sec_close_sva_prefetch()
510 		pci_err(qm->pdev, "failed to close sva prefetch\n");  in sec_close_sva_prefetch()
517 	if (qm->ver < QM_HW_V3)  in sec_enable_clock_gate()
520 	val = readl_relaxed(qm->io_base + SEC_CONTROL_REG);  in sec_enable_clock_gate()
522 	writel_relaxed(val, qm->io_base + SEC_CONTROL_REG);  in sec_enable_clock_gate()
524 	val = readl(qm->io_base + SEC_DYNAMIC_GATE_REG);  in sec_enable_clock_gate()
526 	writel(val, qm->io_base + SEC_DYNAMIC_GATE_REG);  in sec_enable_clock_gate()
528 	val = readl(qm->io_base + SEC_CORE_AUTO_GATE);  in sec_enable_clock_gate()
530 	writel(val, qm->io_base + SEC_CORE_AUTO_GATE);  in sec_enable_clock_gate()
538 	val = readl_relaxed(qm->io_base + SEC_CONTROL_REG);  in sec_disable_clock_gate()
540 	writel_relaxed(val, qm->io_base + SEC_CONTROL_REG);  in sec_disable_clock_gate()
551 	writel_relaxed(0x1, qm->io_base + SEC_MEM_START_INIT_REG);  in sec_engine_init()
553 	ret = readl_relaxed_poll_timeout(qm->io_base + SEC_MEM_INIT_DONE_REG,  in sec_engine_init()
557 		pci_err(qm->pdev, "fail to init sec mem\n");  in sec_engine_init()
561 	reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);  in sec_engine_init()
563 	writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);  in sec_engine_init()
568 	       qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS);  in sec_engine_init()
570 	reg = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CORE_ENABLE_BITMAP, qm->cap_ver);  in sec_engine_init()
571 	writel(reg, qm->io_base + SEC_SAA_EN_REG);  in sec_engine_init()
573 	if (qm->ver < QM_HW_V3) {  in sec_engine_init()
576 			       qm->io_base + SEC_BD_ERR_CHK_EN_REG0);  in sec_engine_init()
580 			       qm->io_base + SEC_BD_ERR_CHK_EN_REG1);  in sec_engine_init()
582 			       qm->io_base + SEC_BD_ERR_CHK_EN_REG3);  in sec_engine_init()
596 	writel(AXUSER_BASE, qm->io_base + QM_ARUSER_M_CFG_1);  in sec_set_user_domain_and_cache()
597 	writel(ARUSER_M_CFG_ENABLE, qm->io_base + QM_ARUSER_M_CFG_ENABLE);  in sec_set_user_domain_and_cache()
598 	writel(AXUSER_BASE, qm->io_base + QM_AWUSER_M_CFG_1);  in sec_set_user_domain_and_cache()
599 	writel(AWUSER_M_CFG_ENABLE, qm->io_base + QM_AWUSER_M_CFG_ENABLE);  in sec_set_user_domain_and_cache()
600 	writel(WUSER_M_CFG_ENABLE, qm->io_base + QM_WUSER_M_CFG_ENABLE);  in sec_set_user_domain_and_cache()
603 	writel(AXI_M_CFG, qm->io_base + QM_AXI_M_CFG);  in sec_set_user_domain_and_cache()
604 	writel(AXI_M_CFG_ENABLE, qm->io_base + QM_AXI_M_CFG_ENABLE);  in sec_set_user_domain_and_cache()
607 	writel(PEH_AXUSER_CFG, qm->io_base + QM_PEH_AXUSER_CFG);  in sec_set_user_domain_and_cache()
608 	writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE);  in sec_set_user_domain_and_cache()
613 	       FIELD_PREP(CQC_CACHE_WB_THRD, 1), qm->io_base + QM_CACHE_CTL);  in sec_set_user_domain_and_cache()
618 /* sec_debug_regs_clear() - clear the sec debug regs */
624 	writel(0x1, qm->io_base + SEC_CTRL_CNT_CLR_CE);  in sec_debug_regs_clear()
626 		readl(qm->io_base + sec_dfx_regs[i].offset);  in sec_debug_regs_clear()
629 	writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE);  in sec_debug_regs_clear()
638 	val1 = readl(qm->io_base + SEC_CONTROL_REG);  in sec_master_ooo_ctrl()
642 					   SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);  in sec_master_ooo_ctrl()
648 	if (qm->ver > QM_HW_V2)  in sec_master_ooo_ctrl()
649 		writel(val2, qm->io_base + SEC_OOO_SHUTDOWN_SEL);  in sec_master_ooo_ctrl()
651 	writel(val1, qm->io_base + SEC_CONTROL_REG);  in sec_master_ooo_ctrl()
658 	if (qm->ver == QM_HW_V1) {  in sec_hw_error_enable()
659 		writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);  in sec_hw_error_enable()
660 		pci_info(qm->pdev, "V1 not support hw error handle\n");  in sec_hw_error_enable()
664 	ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CE_MASK_CAP, qm->cap_ver);  in sec_hw_error_enable()
665 	nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver);  in sec_hw_error_enable()
668 	writel(ce | nfe | SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_CORE_INT_SOURCE);  in sec_hw_error_enable()
671 	writel(ce, qm->io_base + SEC_RAS_CE_REG);  in sec_hw_error_enable()
672 	writel(SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_RAS_FE_REG);  in sec_hw_error_enable()
673 	writel(nfe, qm->io_base + SEC_RAS_NFE_REG);  in sec_hw_error_enable()
679 	writel(ce | nfe | SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_CORE_INT_MASK);  in sec_hw_error_enable()
685 	writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);  in sec_hw_error_disable()
691 	writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG);  in sec_hw_error_disable()
692 	writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG);  in sec_hw_error_disable()
693 	writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG);  in sec_hw_error_disable()
698 	return readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) &  in sec_clear_enable_read()
707 		return -EINVAL;  in sec_clear_enable_write()
709 	tmp = (readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) &  in sec_clear_enable_write()
711 	writel(tmp, qm->io_base + SEC_CTRL_CNT_CLR_CE);  in sec_clear_enable_write()
719 	struct sec_debug_file *file = filp->private_data;  in sec_debug_read()
721 	struct hisi_qm *qm = file->qm;  in sec_debug_read()
729 	spin_lock_irq(&file->lock);  in sec_debug_read()
731 	switch (file->index) {  in sec_debug_read()
739 	spin_unlock_irq(&file->lock);  in sec_debug_read()
746 	spin_unlock_irq(&file->lock);  in sec_debug_read()
748 	return -EINVAL;  in sec_debug_read()
754 	struct sec_debug_file *file = filp->private_data;  in sec_debug_write()
756 	struct hisi_qm *qm = file->qm;  in sec_debug_write()
764 		return -ENOSPC;  in sec_debug_write()
766 	len = simple_write_to_buffer(tbuf, SEC_DBGFS_VAL_MAX_LEN - 1,  in sec_debug_write()
773 		return -EFAULT;  in sec_debug_write()
779 	spin_lock_irq(&file->lock);  in sec_debug_write()
781 	switch (file->index) {  in sec_debug_write()
788 		ret = -EINVAL;  in sec_debug_write()
795 	spin_unlock_irq(&file->lock);  in sec_debug_write()
817 		return -EINVAL;  in sec_debugfs_atomic64_set()
829 	hisi_qm_regs_dump(s, s->private);  in sec_regs_show()
838 	struct dfx_diff_registers *sec_regs = qm->debug.acc_diff_regs;  in sec_core_debug_init()
840 	struct device *dev = &qm->pdev->dev;  in sec_core_debug_init()
841 	struct sec_dfx *dfx = &sec->debug.dfx;  in sec_core_debug_init()
846 	tmp_d = debugfs_create_dir("sec_dfx", qm->debug.debug_root);  in sec_core_debug_init()
850 		return -ENOMEM;  in sec_core_debug_init()
852 	regset->regs = sec_dfx_regs;  in sec_core_debug_init()
853 	regset->nregs = ARRAY_SIZE(sec_dfx_regs);  in sec_core_debug_init()
854 	regset->base = qm->io_base;  in sec_core_debug_init()
855 	regset->dev = dev;  in sec_core_debug_init()
857 	if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF)  in sec_core_debug_init()
859 	if (qm->fun_type == QM_HW_PF && sec_regs)  in sec_core_debug_init()
878 	if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) {  in sec_debug_init()
880 			spin_lock_init(&sec->debug.files[i].lock);  in sec_debug_init()
881 			sec->debug.files[i].index = i;  in sec_debug_init()
882 			sec->debug.files[i].qm = qm;  in sec_debug_init()
885 						  qm->debug.debug_root,  in sec_debug_init()
886 						  sec->debug.files + i,  in sec_debug_init()
896 	struct device *dev = &qm->pdev->dev;  in sec_debugfs_init()
899 	qm->debug.debug_root = debugfs_create_dir(dev_name(dev),  in sec_debugfs_init()
901 	qm->debug.sqe_mask_offset = SEC_SQE_MASK_OFFSET;  in sec_debugfs_init()
902 	qm->debug.sqe_mask_len = SEC_SQE_MASK_LEN;  in sec_debugfs_init()
929 	debugfs_remove_recursive(qm->debug.debug_root);  in sec_debugfs_exit()
934 	struct qm_debug *debug = &qm->debug;  in sec_show_last_regs_init()
937 	debug->last_words = kcalloc(ARRAY_SIZE(sec_dfx_regs),  in sec_show_last_regs_init()
939 	if (!debug->last_words)  in sec_show_last_regs_init()
940 		return -ENOMEM;  in sec_show_last_regs_init()
943 		debug->last_words[i] = readl_relaxed(qm->io_base +  in sec_show_last_regs_init()
951 	struct qm_debug *debug = &qm->debug;  in sec_show_last_regs_uninit()
953 	if (qm->fun_type == QM_HW_VF || !debug->last_words)  in sec_show_last_regs_uninit()
956 	kfree(debug->last_words);  in sec_show_last_regs_uninit()
957 	debug->last_words = NULL;  in sec_show_last_regs_uninit()
962 	struct qm_debug *debug = &qm->debug;  in sec_show_last_dfx_regs()
963 	struct pci_dev *pdev = qm->pdev;  in sec_show_last_dfx_regs()
967 	if (qm->fun_type == QM_HW_VF || !debug->last_words)  in sec_show_last_dfx_regs()
972 		val = readl_relaxed(qm->io_base + sec_dfx_regs[i].offset);  in sec_show_last_dfx_regs()
973 		if (val != debug->last_words[i])  in sec_show_last_dfx_regs()
975 				sec_dfx_regs[i].name, debug->last_words[i], val);  in sec_show_last_dfx_regs()
982 	struct device *dev = &qm->pdev->dev;  in sec_log_hw_error()
985 	while (errs->msg) {  in sec_log_hw_error()
986 		if (errs->int_msk & err_sts) {  in sec_log_hw_error()
988 					errs->msg, errs->int_msk);  in sec_log_hw_error()
990 			if (SEC_CORE_INT_STATUS_M_ECC & errs->int_msk) {  in sec_log_hw_error()
991 				err_val = readl(qm->io_base +  in sec_log_hw_error()
1004 	return readl(qm->io_base + SEC_CORE_INT_STATUS);  in sec_get_hw_err_status()
1009 	writel(err_sts, qm->io_base + SEC_CORE_INT_SOURCE);  in sec_clear_hw_err_status()
1016 	nfe_mask = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver);  in sec_disable_error_report()
1017 	writel(nfe_mask & (~err_type), qm->io_base + SEC_RAS_NFE_REG);  in sec_disable_error_report()
1024 	val = readl(qm->io_base + SEC_CONTROL_REG);  in sec_open_axi_master_ooo()
1025 	writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG);  in sec_open_axi_master_ooo()
1026 	writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG);  in sec_open_axi_master_ooo()
1035 		if (err_status & qm->err_info.ecc_2bits_mask)  in sec_get_err_result()
1036 			qm->err_status.is_dev_ecc_mbit = true;  in sec_get_err_result()
1039 		if (err_status & qm->err_info.dev_reset_mask) {  in sec_get_err_result()
1052 	struct hisi_qm_err_info *err_info = &qm->err_info;  in sec_err_info_init()
1054 	err_info->fe = SEC_RAS_FE_ENB_MSK;  in sec_err_info_init()
1055 	err_info->ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_CE_MASK_CAP, qm->cap_ver);  in sec_err_info_init()
1056 	err_info->nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_NFE_MASK_CAP, qm->cap_ver);  in sec_err_info_init()
1057 	err_info->ecc_2bits_mask = SEC_CORE_INT_STATUS_M_ECC;  in sec_err_info_init()
1058 	err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info,  in sec_err_info_init()
1059 				     SEC_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);  in sec_err_info_init()
1060 	err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info,  in sec_err_info_init()
1061 			SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);  in sec_err_info_init()
1062 	err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info,  in sec_err_info_init()
1063 			SEC_QM_RESET_MASK_CAP, qm->cap_ver);  in sec_err_info_init()
1064 	err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info,  in sec_err_info_init()
1065 			SEC_RESET_MASK_CAP, qm->cap_ver);  in sec_err_info_init()
1066 	err_info->msi_wr_port = BIT(0);  in sec_err_info_init()
1067 	err_info->acpi_rst = "SRST";  in sec_err_info_init()
1086 	struct hisi_qm *qm = &sec->qm;  in sec_pf_probe_init()
1098 		pci_err(qm->pdev, "Failed to init last word regs!\n");  in sec_pf_probe_init()
1106 	struct pci_dev *pdev = qm->pdev;  in sec_pre_store_cap_reg()
1110 	sec_cap = devm_kzalloc(&pdev->dev, sizeof(*sec_cap) * size, GFP_KERNEL);  in sec_pre_store_cap_reg()
1112 		return -ENOMEM;  in sec_pre_store_cap_reg()
1117 				     sec_pre_store_caps[i], qm->cap_ver);  in sec_pre_store_cap_reg()
1120 	qm->cap_tables.dev_cap_table = sec_cap;  in sec_pre_store_cap_reg()
1130 	qm->pdev = pdev;  in sec_qm_init()
1131 	qm->ver = pdev->revision;  in sec_qm_init()
1132 	qm->mode = uacce_mode;  in sec_qm_init()
1133 	qm->sqe_size = SEC_SQE_SIZE;  in sec_qm_init()
1134 	qm->dev_name = sec_name;  in sec_qm_init()
1136 	qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) ?  in sec_qm_init()
1138 	if (qm->fun_type == QM_HW_PF) {  in sec_qm_init()
1139 		qm->qp_base = SEC_PF_DEF_Q_BASE;  in sec_qm_init()
1140 		qm->qp_num = pf_q_num;  in sec_qm_init()
1141 		qm->debug.curr_qm_qp_num = pf_q_num;  in sec_qm_init()
1142 		qm->qm_list = &sec_devices;  in sec_qm_init()
1143 		qm->err_ini = &sec_err_ini;  in sec_qm_init()
1145 			set_bit(QM_MODULE_PARAM, &qm->misc_ctl);  in sec_qm_init()
1146 	} else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) {  in sec_qm_init()
1148 		 * have no way to get qm configure in VM in v1 hardware,  in sec_qm_init()
1150 		 * to trigger only one VF in v1 hardware.  in sec_qm_init()
1153 		qm->qp_base = SEC_PF_DEF_Q_NUM;  in sec_qm_init()
1154 		qm->qp_num = SEC_QUEUE_NUM_V1 - SEC_PF_DEF_Q_NUM;  in sec_qm_init()
1159 		pci_err(qm->pdev, "Failed to init sec qm configures!\n");  in sec_qm_init()
1166 		pci_err(qm->pdev, "Failed to pre-store capability registers!\n");  in sec_qm_init()
1174 		pci_err(qm->pdev, "Failed to set sec algs!\n");  in sec_qm_init()
1189 	struct hisi_qm *qm = &sec->qm;  in sec_probe_init()
1192 	if (qm->fun_type == QM_HW_PF) {  in sec_probe_init()
1197 		if (qm->ver >= QM_HW_V3) {  in sec_probe_init()
1199 			qm->type_rate = type_rate;  in sec_probe_init()
1208 	if (qm->fun_type == QM_HW_VF)  in sec_probe_uninit()
1220 	struct device *dev = &sec->qm.pdev->dev;  in sec_iommu_used_check()
1225 	sec->iommu_used = false;  in sec_iommu_used_check()
1227 		if (domain->type & __IOMMU_DOMAIN_PAGING)  in sec_iommu_used_check()
1228 			sec->iommu_used = true;  in sec_iommu_used_check()
1229 		dev_info(dev, "SMMU Opened, the iommu type = %u\n",  in sec_iommu_used_check()
1230 			domain->type);  in sec_iommu_used_check()
1240 	sec = devm_kzalloc(&pdev->dev, sizeof(*sec), GFP_KERNEL);  in sec_probe()
1242 		return -ENOMEM;  in sec_probe()
1244 	qm = &sec->qm;  in sec_probe()
1251 	sec->ctx_q_num = ctx_q_num;  in sec_probe()
1270 	if (qm->qp_num >= ctx_q_num) {  in sec_probe()
1277 		pci_warn(qm->pdev,  in sec_probe()
1281 	if (qm->uacce) {  in sec_probe()
1282 		ret = uacce_register(qm->uacce);  in sec_probe()
1289 	if (qm->fun_type == QM_HW_PF && vfs_num) {  in sec_probe()
1300 	if (qm->qp_num >= ctx_q_num)  in sec_probe()
1318 	if (qm->qp_num >= ctx_q_num)  in sec_remove()
1321 	if (qm->fun_type == QM_HW_PF && qm->vfs_num)  in sec_remove()