644 static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val)  in hifn_write_1()  function
674 	hifn_write_1(dev, HIFN_1_DMA_CSR,  in hifn_stop_device()
678 	hifn_write_1(dev, HIFN_1_DMA_IER, 0);  in hifn_stop_device()
688 	hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |  in hifn_reset_dma()
696 		hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);  in hifn_reset_dma()
699 		hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE |  in hifn_reset_dma()
704 	hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |  in hifn_reset_dma()
803 	hifn_write_1(dev, HIFN_1_PUB_RESET, hifn_read_1(dev, HIFN_1_PUB_RESET) |  in hifn_init_pubrng()
816 		hifn_write_1(dev, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);  in hifn_init_pubrng()
818 		hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);  in hifn_init_pubrng()
825 	hifn_write_1(dev, HIFN_1_RNG_CONFIG,  in hifn_init_pubrng()
858 	hifn_write_1(dev, HIFN_1_DMA_CNFG,  in hifn_enable_crypto()
864 	hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0);  in hifn_enable_crypto()
869 		hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, addr);  in hifn_enable_crypto()
873 	hifn_write_1(dev, HIFN_1_DMA_CNFG, dmacfg);  in hifn_enable_crypto()
950 	hifn_write_1(dev, HIFN_1_PLL, pllcfg |  in hifn_init_pll()
957 	hifn_write_1(dev, HIFN_1_PLL, pllcfg |  in hifn_init_pll()
961 	hifn_write_1(dev, HIFN_1_PLL, pllcfg |  in hifn_init_pll()
983 	hifn_write_1(dev, HIFN_1_DMA_CRAR, dptr +  in hifn_init_registers()
985 	hifn_write_1(dev, HIFN_1_DMA_SRAR, dptr +  in hifn_init_registers()
987 	hifn_write_1(dev, HIFN_1_DMA_DRAR, dptr +  in hifn_init_registers()
989 	hifn_write_1(dev, HIFN_1_DMA_RRAR, dptr +  in hifn_init_registers()
994 	hifn_write_1(dev, HIFN_1_DMA_CSR,  in hifn_init_registers()
1008 	hifn_write_1(dev, HIFN_1_DMA_CSR,  in hifn_init_registers()
1030 	hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);  in hifn_init_registers()
1043 	hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |  in hifn_init_registers()
1095 		hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);  in hifn_setup_crypto_command()
1222 		hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA);  in hifn_setup_cmd_desc()
1258 		hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA);  in hifn_setup_src_desc()
1285 		hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA);  in hifn_setup_res_desc()
1315 		hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA);  in hifn_setup_dst_desc()
1806 			hifn_write_1(dev, HIFN_1_DMA_CSR, r);  in hifn_work()
1866 	hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg);  in hifn_interrupt()
1871 		hifn_write_1(dev, HIFN_1_PUB_STATUS,  in hifn_interrupt()
1884 		hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER |  in hifn_interrupt()
1904 		hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);  in hifn_interrupt()