Lines Matching refs:HIFN_1_DMA_CSR
174 #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ macro
674 hifn_write_1(dev, HIFN_1_DMA_CSR, in hifn_stop_device()
994 hifn_write_1(dev, HIFN_1_DMA_CSR, in hifn_init_registers()
1008 hifn_write_1(dev, HIFN_1_DMA_CSR, in hifn_init_registers()
1022 hifn_read_1(dev, HIFN_1_DMA_CSR); in hifn_init_registers()
1222 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); in hifn_setup_cmd_desc()
1258 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); in hifn_setup_src_desc()
1285 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); in hifn_setup_res_desc()
1315 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA); in hifn_setup_dst_desc()
1806 hifn_write_1(dev, HIFN_1_DMA_CSR, r); in hifn_work()
1855 dmacsr = hifn_read_1(dev, HIFN_1_DMA_CSR); in hifn_interrupt()
1866 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg); in hifn_interrupt()
1884 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER | in hifn_interrupt()