Lines Matching refs:idx
342 int idx) in cc_fin_result() argument
350 hw_desc_init(&desc[idx]); in cc_fin_result()
351 set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode); in cc_fin_result()
352 set_dout_dlli(&desc[idx], state->digest_result_dma_addr, digestsize, in cc_fin_result()
354 set_queue_last_ind(ctx->drvdata, &desc[idx]); in cc_fin_result()
355 set_flow_mode(&desc[idx], S_HASH_to_DOUT); in cc_fin_result()
356 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); in cc_fin_result()
357 set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); in cc_fin_result()
358 cc_set_endianity(ctx->hash_mode, &desc[idx]); in cc_fin_result()
359 idx++; in cc_fin_result()
361 return idx; in cc_fin_result()
365 int idx) in cc_fin_hmac() argument
373 hw_desc_init(&desc[idx]); in cc_fin_hmac()
374 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_fin_hmac()
375 set_dout_dlli(&desc[idx], state->digest_buff_dma_addr, digestsize, in cc_fin_hmac()
377 set_flow_mode(&desc[idx], S_HASH_to_DOUT); in cc_fin_hmac()
378 cc_set_endianity(ctx->hash_mode, &desc[idx]); in cc_fin_hmac()
379 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); in cc_fin_hmac()
380 idx++; in cc_fin_hmac()
383 hw_desc_init(&desc[idx]); in cc_fin_hmac()
384 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_fin_hmac()
385 set_din_type(&desc[idx], DMA_DLLI, state->opad_digest_dma_addr, in cc_fin_hmac()
387 set_flow_mode(&desc[idx], S_DIN_to_HASH); in cc_fin_hmac()
388 set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); in cc_fin_hmac()
389 idx++; in cc_fin_hmac()
392 hw_desc_init(&desc[idx]); in cc_fin_hmac()
393 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_fin_hmac()
394 set_din_sram(&desc[idx], in cc_fin_hmac()
397 set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); in cc_fin_hmac()
398 set_flow_mode(&desc[idx], S_DIN_to_HASH); in cc_fin_hmac()
399 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); in cc_fin_hmac()
400 idx++; in cc_fin_hmac()
403 hw_desc_init(&desc[idx]); in cc_fin_hmac()
404 set_din_no_dma(&desc[idx], 0, 0xfffff0); in cc_fin_hmac()
405 set_dout_no_dma(&desc[idx], 0, 0, 1); in cc_fin_hmac()
406 idx++; in cc_fin_hmac()
409 hw_desc_init(&desc[idx]); in cc_fin_hmac()
410 set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, in cc_fin_hmac()
412 set_flow_mode(&desc[idx], DIN_HASH); in cc_fin_hmac()
413 idx++; in cc_fin_hmac()
415 return idx; in cc_fin_hmac()
432 int idx = 0; in cc_hash_digest() local
467 hw_desc_init(&desc[idx]); in cc_hash_digest()
468 set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode); in cc_hash_digest()
470 set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, in cc_hash_digest()
475 set_din_sram(&desc[idx], larval_digest_addr, in cc_hash_digest()
478 set_flow_mode(&desc[idx], S_DIN_to_HASH); in cc_hash_digest()
479 set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); in cc_hash_digest()
480 idx++; in cc_hash_digest()
483 hw_desc_init(&desc[idx]); in cc_hash_digest()
484 set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode); in cc_hash_digest()
487 set_din_type(&desc[idx], DMA_DLLI, in cc_hash_digest()
491 set_din_const(&desc[idx], 0, ctx->hash_len); in cc_hash_digest()
493 set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); in cc_hash_digest()
495 set_cipher_do(&desc[idx], DO_PAD); in cc_hash_digest()
497 set_flow_mode(&desc[idx], S_DIN_to_HASH); in cc_hash_digest()
498 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); in cc_hash_digest()
499 idx++; in cc_hash_digest()
501 cc_set_desc(state, ctx, DIN_HASH, desc, false, &idx); in cc_hash_digest()
505 hw_desc_init(&desc[idx]); in cc_hash_digest()
506 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_hash_digest()
507 set_dout_dlli(&desc[idx], state->digest_buff_dma_addr, in cc_hash_digest()
509 set_flow_mode(&desc[idx], S_HASH_to_DOUT); in cc_hash_digest()
510 set_setup_mode(&desc[idx], SETUP_WRITE_STATE1); in cc_hash_digest()
511 set_cipher_do(&desc[idx], DO_PAD); in cc_hash_digest()
512 idx++; in cc_hash_digest()
514 idx = cc_fin_hmac(desc, req, idx); in cc_hash_digest()
517 idx = cc_fin_result(desc, req, idx); in cc_hash_digest()
519 rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base); in cc_hash_digest()
530 struct ahash_req_ctx *state, unsigned int idx) in cc_restore_hash() argument
533 hw_desc_init(&desc[idx]); in cc_restore_hash()
534 set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode); in cc_restore_hash()
535 set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, in cc_restore_hash()
537 set_flow_mode(&desc[idx], S_DIN_to_HASH); in cc_restore_hash()
538 set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); in cc_restore_hash()
539 idx++; in cc_restore_hash()
542 hw_desc_init(&desc[idx]); in cc_restore_hash()
543 set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode); in cc_restore_hash()
544 set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); in cc_restore_hash()
545 set_din_type(&desc[idx], DMA_DLLI, state->digest_bytes_len_dma_addr, in cc_restore_hash()
547 set_flow_mode(&desc[idx], S_DIN_to_HASH); in cc_restore_hash()
548 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); in cc_restore_hash()
549 idx++; in cc_restore_hash()
551 cc_set_desc(state, ctx, DIN_HASH, desc, false, &idx); in cc_restore_hash()
553 return idx; in cc_restore_hash()
567 u32 idx = 0; in cc_hash_update() local
602 idx = cc_restore_hash(desc, ctx, state, idx); in cc_hash_update()
605 hw_desc_init(&desc[idx]); in cc_hash_update()
606 set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode); in cc_hash_update()
607 set_dout_dlli(&desc[idx], state->digest_buff_dma_addr, in cc_hash_update()
609 set_flow_mode(&desc[idx], S_HASH_to_DOUT); in cc_hash_update()
610 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); in cc_hash_update()
611 idx++; in cc_hash_update()
614 hw_desc_init(&desc[idx]); in cc_hash_update()
615 set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode); in cc_hash_update()
616 set_dout_dlli(&desc[idx], state->digest_bytes_len_dma_addr, in cc_hash_update()
618 set_queue_last_ind(ctx->drvdata, &desc[idx]); in cc_hash_update()
619 set_flow_mode(&desc[idx], S_HASH_to_DOUT); in cc_hash_update()
620 set_setup_mode(&desc[idx], SETUP_WRITE_STATE1); in cc_hash_update()
621 idx++; in cc_hash_update()
623 rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base); in cc_hash_update()
645 unsigned int idx = 0; in cc_do_finup() local
674 idx = cc_restore_hash(desc, ctx, state, idx); in cc_do_finup()
677 hw_desc_init(&desc[idx]); in cc_do_finup()
678 set_cipher_do(&desc[idx], DO_PAD); in cc_do_finup()
679 set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode); in cc_do_finup()
680 set_dout_dlli(&desc[idx], state->digest_bytes_len_dma_addr, in cc_do_finup()
682 set_setup_mode(&desc[idx], SETUP_WRITE_STATE1); in cc_do_finup()
683 set_flow_mode(&desc[idx], S_HASH_to_DOUT); in cc_do_finup()
684 idx++; in cc_do_finup()
687 idx = cc_fin_hmac(desc, req, idx); in cc_do_finup()
689 idx = cc_fin_result(desc, req, idx); in cc_do_finup()
691 rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base); in cc_do_finup()
734 int i, idx = 0, rc = 0; in cc_hash_setkey() local
775 hw_desc_init(&desc[idx]); in cc_hash_setkey()
776 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_hash_setkey()
777 set_din_sram(&desc[idx], larval_addr, in cc_hash_setkey()
779 set_flow_mode(&desc[idx], S_DIN_to_HASH); in cc_hash_setkey()
780 set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); in cc_hash_setkey()
781 idx++; in cc_hash_setkey()
784 hw_desc_init(&desc[idx]); in cc_hash_setkey()
785 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_hash_setkey()
786 set_din_const(&desc[idx], 0, ctx->hash_len); in cc_hash_setkey()
787 set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); in cc_hash_setkey()
788 set_flow_mode(&desc[idx], S_DIN_to_HASH); in cc_hash_setkey()
789 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); in cc_hash_setkey()
790 idx++; in cc_hash_setkey()
792 hw_desc_init(&desc[idx]); in cc_hash_setkey()
793 set_din_type(&desc[idx], DMA_DLLI, in cc_hash_setkey()
796 set_flow_mode(&desc[idx], DIN_HASH); in cc_hash_setkey()
797 idx++; in cc_hash_setkey()
800 hw_desc_init(&desc[idx]); in cc_hash_setkey()
801 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_hash_setkey()
802 set_dout_dlli(&desc[idx], ctx->opad_tmp_keys_dma_addr, in cc_hash_setkey()
804 set_flow_mode(&desc[idx], S_HASH_to_DOUT); in cc_hash_setkey()
805 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); in cc_hash_setkey()
806 set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); in cc_hash_setkey()
807 cc_set_endianity(ctx->hash_mode, &desc[idx]); in cc_hash_setkey()
808 idx++; in cc_hash_setkey()
810 hw_desc_init(&desc[idx]); in cc_hash_setkey()
811 set_din_const(&desc[idx], 0, (blocksize - digestsize)); in cc_hash_setkey()
812 set_flow_mode(&desc[idx], BYPASS); in cc_hash_setkey()
813 set_dout_dlli(&desc[idx], in cc_hash_setkey()
817 idx++; in cc_hash_setkey()
819 hw_desc_init(&desc[idx]); in cc_hash_setkey()
820 set_din_type(&desc[idx], DMA_DLLI, in cc_hash_setkey()
823 set_flow_mode(&desc[idx], BYPASS); in cc_hash_setkey()
824 set_dout_dlli(&desc[idx], ctx->opad_tmp_keys_dma_addr, in cc_hash_setkey()
826 idx++; in cc_hash_setkey()
829 hw_desc_init(&desc[idx]); in cc_hash_setkey()
830 set_din_const(&desc[idx], 0, in cc_hash_setkey()
832 set_flow_mode(&desc[idx], BYPASS); in cc_hash_setkey()
833 set_dout_dlli(&desc[idx], in cc_hash_setkey()
837 idx++; in cc_hash_setkey()
841 hw_desc_init(&desc[idx]); in cc_hash_setkey()
842 set_din_const(&desc[idx], 0, blocksize); in cc_hash_setkey()
843 set_flow_mode(&desc[idx], BYPASS); in cc_hash_setkey()
844 set_dout_dlli(&desc[idx], (ctx->opad_tmp_keys_dma_addr), in cc_hash_setkey()
846 idx++; in cc_hash_setkey()
849 rc = cc_send_sync_request(ctx->drvdata, &cc_req, desc, idx); in cc_hash_setkey()
856 for (idx = 0, i = 0; i < 2; i++) { in cc_hash_setkey()
858 hw_desc_init(&desc[idx]); in cc_hash_setkey()
859 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_hash_setkey()
860 set_din_sram(&desc[idx], larval_addr, ctx->inter_digestsize); in cc_hash_setkey()
861 set_flow_mode(&desc[idx], S_DIN_to_HASH); in cc_hash_setkey()
862 set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); in cc_hash_setkey()
863 idx++; in cc_hash_setkey()
866 hw_desc_init(&desc[idx]); in cc_hash_setkey()
867 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_hash_setkey()
868 set_din_const(&desc[idx], 0, ctx->hash_len); in cc_hash_setkey()
869 set_flow_mode(&desc[idx], S_DIN_to_HASH); in cc_hash_setkey()
870 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); in cc_hash_setkey()
871 idx++; in cc_hash_setkey()
874 hw_desc_init(&desc[idx]); in cc_hash_setkey()
875 set_xor_val(&desc[idx], hmac_pad_const[i]); in cc_hash_setkey()
876 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_hash_setkey()
877 set_flow_mode(&desc[idx], S_DIN_to_HASH); in cc_hash_setkey()
878 set_setup_mode(&desc[idx], SETUP_LOAD_STATE1); in cc_hash_setkey()
879 idx++; in cc_hash_setkey()
882 hw_desc_init(&desc[idx]); in cc_hash_setkey()
883 set_din_type(&desc[idx], DMA_DLLI, ctx->opad_tmp_keys_dma_addr, in cc_hash_setkey()
885 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_hash_setkey()
886 set_xor_active(&desc[idx]); in cc_hash_setkey()
887 set_flow_mode(&desc[idx], DIN_HASH); in cc_hash_setkey()
888 idx++; in cc_hash_setkey()
893 hw_desc_init(&desc[idx]); in cc_hash_setkey()
894 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_hash_setkey()
896 set_dout_dlli(&desc[idx], ctx->opad_tmp_keys_dma_addr, in cc_hash_setkey()
899 set_dout_dlli(&desc[idx], ctx->digest_buff_dma_addr, in cc_hash_setkey()
901 set_flow_mode(&desc[idx], S_HASH_to_DOUT); in cc_hash_setkey()
902 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); in cc_hash_setkey()
903 idx++; in cc_hash_setkey()
906 rc = cc_send_sync_request(ctx->drvdata, &cc_req, desc, idx); in cc_hash_setkey()
928 unsigned int idx = 0; in cc_xcbc_setkey() local
961 hw_desc_init(&desc[idx]); in cc_xcbc_setkey()
962 set_din_type(&desc[idx], DMA_DLLI, ctx->key_params.key_dma_addr, in cc_xcbc_setkey()
964 set_cipher_mode(&desc[idx], DRV_CIPHER_ECB); in cc_xcbc_setkey()
965 set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); in cc_xcbc_setkey()
966 set_key_size_aes(&desc[idx], keylen); in cc_xcbc_setkey()
967 set_flow_mode(&desc[idx], S_DIN_to_AES); in cc_xcbc_setkey()
968 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); in cc_xcbc_setkey()
969 idx++; in cc_xcbc_setkey()
971 hw_desc_init(&desc[idx]); in cc_xcbc_setkey()
972 set_din_const(&desc[idx], 0x01010101, CC_AES_128_BIT_KEY_SIZE); in cc_xcbc_setkey()
973 set_flow_mode(&desc[idx], DIN_AES_DOUT); in cc_xcbc_setkey()
974 set_dout_dlli(&desc[idx], in cc_xcbc_setkey()
977 idx++; in cc_xcbc_setkey()
979 hw_desc_init(&desc[idx]); in cc_xcbc_setkey()
980 set_din_const(&desc[idx], 0x02020202, CC_AES_128_BIT_KEY_SIZE); in cc_xcbc_setkey()
981 set_flow_mode(&desc[idx], DIN_AES_DOUT); in cc_xcbc_setkey()
982 set_dout_dlli(&desc[idx], in cc_xcbc_setkey()
985 idx++; in cc_xcbc_setkey()
987 hw_desc_init(&desc[idx]); in cc_xcbc_setkey()
988 set_din_const(&desc[idx], 0x03030303, CC_AES_128_BIT_KEY_SIZE); in cc_xcbc_setkey()
989 set_flow_mode(&desc[idx], DIN_AES_DOUT); in cc_xcbc_setkey()
990 set_dout_dlli(&desc[idx], in cc_xcbc_setkey()
993 idx++; in cc_xcbc_setkey()
995 rc = cc_send_sync_request(ctx->drvdata, &cc_req, desc, idx); in cc_xcbc_setkey()
1160 u32 idx = 0; in cc_mac_update() local
1189 cc_setup_xcbc(req, desc, &idx); in cc_mac_update()
1191 cc_setup_cmac(req, desc, &idx); in cc_mac_update()
1193 cc_set_desc(state, ctx, DIN_AES_DOUT, desc, true, &idx); in cc_mac_update()
1196 hw_desc_init(&desc[idx]); in cc_mac_update()
1197 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_mac_update()
1198 set_dout_dlli(&desc[idx], state->digest_buff_dma_addr, in cc_mac_update()
1200 set_queue_last_ind(ctx->drvdata, &desc[idx]); in cc_mac_update()
1201 set_flow_mode(&desc[idx], S_AES_to_DOUT); in cc_mac_update()
1202 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); in cc_mac_update()
1203 idx++; in cc_mac_update()
1209 rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base); in cc_mac_update()
1226 int idx = 0; in cc_mac_final() local
1269 hw_desc_init(&desc[idx]); in cc_mac_final()
1270 set_cipher_mode(&desc[idx], DRV_CIPHER_ECB); in cc_mac_final()
1271 set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_DECRYPT); in cc_mac_final()
1272 set_din_type(&desc[idx], DMA_DLLI, in cc_mac_final()
1275 set_key_size_aes(&desc[idx], key_len); in cc_mac_final()
1276 set_flow_mode(&desc[idx], S_DIN_to_AES); in cc_mac_final()
1277 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); in cc_mac_final()
1278 idx++; in cc_mac_final()
1283 hw_desc_init(&desc[idx]); in cc_mac_final()
1284 set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, in cc_mac_final()
1286 set_dout_dlli(&desc[idx], state->digest_buff_dma_addr, in cc_mac_final()
1288 set_flow_mode(&desc[idx], DIN_AES_DOUT); in cc_mac_final()
1289 idx++; in cc_mac_final()
1292 hw_desc_init(&desc[idx]); in cc_mac_final()
1293 set_din_no_dma(&desc[idx], 0, 0xfffff0); in cc_mac_final()
1294 set_dout_no_dma(&desc[idx], 0, 0, 1); in cc_mac_final()
1295 idx++; in cc_mac_final()
1299 cc_setup_xcbc(req, desc, &idx); in cc_mac_final()
1301 cc_setup_cmac(req, desc, &idx); in cc_mac_final()
1304 hw_desc_init(&desc[idx]); in cc_mac_final()
1305 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_mac_final()
1306 set_key_size_aes(&desc[idx], key_len); in cc_mac_final()
1307 set_cmac_size0_mode(&desc[idx]); in cc_mac_final()
1308 set_flow_mode(&desc[idx], S_DIN_to_AES); in cc_mac_final()
1309 idx++; in cc_mac_final()
1311 cc_set_desc(state, ctx, DIN_AES_DOUT, desc, false, &idx); in cc_mac_final()
1313 hw_desc_init(&desc[idx]); in cc_mac_final()
1314 set_din_const(&desc[idx], 0x00, CC_AES_BLOCK_SIZE); in cc_mac_final()
1315 set_flow_mode(&desc[idx], DIN_AES_DOUT); in cc_mac_final()
1316 idx++; in cc_mac_final()
1320 hw_desc_init(&desc[idx]); in cc_mac_final()
1321 set_dout_dlli(&desc[idx], state->digest_result_dma_addr, in cc_mac_final()
1323 set_queue_last_ind(ctx->drvdata, &desc[idx]); in cc_mac_final()
1324 set_flow_mode(&desc[idx], S_AES_to_DOUT); in cc_mac_final()
1325 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); in cc_mac_final()
1326 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_mac_final()
1327 idx++; in cc_mac_final()
1329 rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base); in cc_mac_final()
1347 int idx = 0; in cc_mac_finup() local
1383 cc_setup_xcbc(req, desc, &idx); in cc_mac_finup()
1386 cc_setup_cmac(req, desc, &idx); in cc_mac_finup()
1390 hw_desc_init(&desc[idx]); in cc_mac_finup()
1391 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_mac_finup()
1392 set_key_size_aes(&desc[idx], key_len); in cc_mac_finup()
1393 set_cmac_size0_mode(&desc[idx]); in cc_mac_finup()
1394 set_flow_mode(&desc[idx], S_DIN_to_AES); in cc_mac_finup()
1395 idx++; in cc_mac_finup()
1397 cc_set_desc(state, ctx, DIN_AES_DOUT, desc, false, &idx); in cc_mac_finup()
1401 hw_desc_init(&desc[idx]); in cc_mac_finup()
1402 set_dout_dlli(&desc[idx], state->digest_result_dma_addr, in cc_mac_finup()
1404 set_queue_last_ind(ctx->drvdata, &desc[idx]); in cc_mac_finup()
1405 set_flow_mode(&desc[idx], S_AES_to_DOUT); in cc_mac_finup()
1406 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); in cc_mac_finup()
1407 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_mac_finup()
1408 idx++; in cc_mac_finup()
1410 rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base); in cc_mac_finup()
1430 unsigned int idx = 0; in cc_mac_digest() local
1461 cc_setup_xcbc(req, desc, &idx); in cc_mac_digest()
1464 cc_setup_cmac(req, desc, &idx); in cc_mac_digest()
1468 hw_desc_init(&desc[idx]); in cc_mac_digest()
1469 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_mac_digest()
1470 set_key_size_aes(&desc[idx], key_len); in cc_mac_digest()
1471 set_cmac_size0_mode(&desc[idx]); in cc_mac_digest()
1472 set_flow_mode(&desc[idx], S_DIN_to_AES); in cc_mac_digest()
1473 idx++; in cc_mac_digest()
1475 cc_set_desc(state, ctx, DIN_AES_DOUT, desc, false, &idx); in cc_mac_digest()
1479 hw_desc_init(&desc[idx]); in cc_mac_digest()
1480 set_dout_dlli(&desc[idx], state->digest_result_dma_addr, in cc_mac_digest()
1482 set_queue_last_ind(ctx->drvdata, &desc[idx]); in cc_mac_digest()
1483 set_flow_mode(&desc[idx], S_AES_to_DOUT); in cc_mac_digest()
1484 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); in cc_mac_digest()
1485 set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); in cc_mac_digest()
1486 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_mac_digest()
1487 idx++; in cc_mac_digest()
1489 rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base); in cc_mac_digest()
2075 unsigned int idx = *seq_size; in cc_setup_xcbc() local
2081 hw_desc_init(&desc[idx]); in cc_setup_xcbc()
2082 set_din_type(&desc[idx], DMA_DLLI, (ctx->opad_tmp_keys_dma_addr + in cc_setup_xcbc()
2085 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); in cc_setup_xcbc()
2086 set_hash_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC, ctx->hash_mode); in cc_setup_xcbc()
2087 set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); in cc_setup_xcbc()
2088 set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE); in cc_setup_xcbc()
2089 set_flow_mode(&desc[idx], S_DIN_to_AES); in cc_setup_xcbc()
2090 idx++; in cc_setup_xcbc()
2093 hw_desc_init(&desc[idx]); in cc_setup_xcbc()
2094 set_din_type(&desc[idx], DMA_DLLI, in cc_setup_xcbc()
2097 set_setup_mode(&desc[idx], SETUP_LOAD_STATE1); in cc_setup_xcbc()
2098 set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC); in cc_setup_xcbc()
2099 set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); in cc_setup_xcbc()
2100 set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE); in cc_setup_xcbc()
2101 set_flow_mode(&desc[idx], S_DIN_to_AES); in cc_setup_xcbc()
2102 idx++; in cc_setup_xcbc()
2105 hw_desc_init(&desc[idx]); in cc_setup_xcbc()
2106 set_din_type(&desc[idx], DMA_DLLI, in cc_setup_xcbc()
2109 set_setup_mode(&desc[idx], SETUP_LOAD_STATE2); in cc_setup_xcbc()
2110 set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC); in cc_setup_xcbc()
2111 set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); in cc_setup_xcbc()
2112 set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE); in cc_setup_xcbc()
2113 set_flow_mode(&desc[idx], S_DIN_to_AES); in cc_setup_xcbc()
2114 idx++; in cc_setup_xcbc()
2117 hw_desc_init(&desc[idx]); in cc_setup_xcbc()
2118 set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, in cc_setup_xcbc()
2120 set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); in cc_setup_xcbc()
2121 set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC); in cc_setup_xcbc()
2122 set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); in cc_setup_xcbc()
2123 set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE); in cc_setup_xcbc()
2124 set_flow_mode(&desc[idx], S_DIN_to_AES); in cc_setup_xcbc()
2125 idx++; in cc_setup_xcbc()
2126 *seq_size = idx; in cc_setup_xcbc()
2132 unsigned int idx = *seq_size; in cc_setup_cmac() local
2138 hw_desc_init(&desc[idx]); in cc_setup_cmac()
2139 set_din_type(&desc[idx], DMA_DLLI, ctx->opad_tmp_keys_dma_addr, in cc_setup_cmac()
2142 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); in cc_setup_cmac()
2143 set_cipher_mode(&desc[idx], DRV_CIPHER_CMAC); in cc_setup_cmac()
2144 set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); in cc_setup_cmac()
2145 set_key_size_aes(&desc[idx], ctx->key_params.keylen); in cc_setup_cmac()
2146 set_flow_mode(&desc[idx], S_DIN_to_AES); in cc_setup_cmac()
2147 idx++; in cc_setup_cmac()
2150 hw_desc_init(&desc[idx]); in cc_setup_cmac()
2151 set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, in cc_setup_cmac()
2153 set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); in cc_setup_cmac()
2154 set_cipher_mode(&desc[idx], DRV_CIPHER_CMAC); in cc_setup_cmac()
2155 set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); in cc_setup_cmac()
2156 set_key_size_aes(&desc[idx], ctx->key_params.keylen); in cc_setup_cmac()
2157 set_flow_mode(&desc[idx], S_DIN_to_AES); in cc_setup_cmac()
2158 idx++; in cc_setup_cmac()
2159 *seq_size = idx; in cc_setup_cmac()
2167 unsigned int idx = *seq_size; in cc_set_desc() local
2171 hw_desc_init(&desc[idx]); in cc_set_desc()
2172 set_din_type(&desc[idx], DMA_DLLI, in cc_set_desc()
2175 set_flow_mode(&desc[idx], flow_mode); in cc_set_desc()
2176 idx++; in cc_set_desc()
2184 hw_desc_init(&desc[idx]); in cc_set_desc()
2185 set_din_type(&desc[idx], DMA_DLLI, in cc_set_desc()
2188 set_dout_sram(&desc[idx], ctx->drvdata->mlli_sram_addr, in cc_set_desc()
2190 set_flow_mode(&desc[idx], BYPASS); in cc_set_desc()
2191 idx++; in cc_set_desc()
2193 hw_desc_init(&desc[idx]); in cc_set_desc()
2194 set_din_type(&desc[idx], DMA_MLLI, in cc_set_desc()
2197 set_flow_mode(&desc[idx], flow_mode); in cc_set_desc()
2198 idx++; in cc_set_desc()
2201 set_din_not_last_indication(&desc[(idx - 1)]); in cc_set_desc()
2203 *seq_size = idx; in cc_set_desc()